From 2b1f7875bb8c3a761dfb9db21706f918b58be9c3 Mon Sep 17 00:00:00 2001 From: Sergiusz Bazanski Date: Sun, 22 Jul 2018 13:42:07 +0100 Subject: ice40: Implement emitting PLLs --- ice40/chipdb.py | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'ice40/chipdb.py') diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 0e8e3ba7..63f08e36 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -184,6 +184,8 @@ def wire_type(name): wt = "LOCAL" elif name in ("WCLK", "WCLKE", "WE", "RCLK", "RCLKE", "RE"): wt = "LOCAL" + elif name in ("PLLOUT_A", "PLLOUT_B"): + wt = "LOCAL" if wt is None: print("No type for wire: %s (%s)" % (longname, name), file=sys.stderr) @@ -591,6 +593,43 @@ def is_ec_output(ec_entry): if "glb_netwk_" in wirename: return True return False +def is_ec_pll_clock_output(ec, ec_entry): + return ec[0] == 'PLL' and ec_entry[0] in ('PLLOUT_A', 'PLLOUT_B') + +def add_pll_clock_output(bel, ec, ec_entry): + #print('add_pll_clock_output', ec, ec_entry) + pll_x, pll_y, pll_z = ec[1], ec[2], ec[3] + port = ec_entry[0] + io_x, io_y, io_z = ec_entry[1] + io_z = int(io_z) + + global num_wires + wire_idx = num_wires + num_wires = num_wires + 1 + + wire_xy[wire_idx] = [(pll_x, pll_y)] + + wire_names_r[wire_idx] = (pll_x, pll_y, port) + wire_names[(pll_x, pll_y, port)] = wire_idx + wire_segments[wire_idx] = { + (pll_x, pll_y): port, + (io_x, io_y): 'PLLIN', + } + + wire_downhill_belports[wire_idx] = {(bel, port),} + bel_wires[bel].append((wire_idx, port)) + + io_wire = wire_names[(io_x, io_y, 'io_{}/D_IN_0'.format(io_z))] + wire_downhill[wire_idx] = {io_wire,} + if io_wire not in wire_uphill: + wire_uphill[io_wire] = set() + wire_uphill[io_wire].add(wire_idx) + + switches.append((io_x, io_y, 0, [])) + switchnum = len(switches) - 1 + pip_xy[(wire_idx, io_wire)] = (io_x, io_y, 0, switchnum) + + def add_bel_ec(ec): ectype, x, y, z = ec bel = len(bel_name) @@ -605,6 +644,8 @@ def add_bel_ec(ec): add_bel_output(bel, wire_names[entry[1]], entry[0]) else: add_bel_input(bel, wire_names[entry[1]], entry[0]) + elif is_ec_pll_clock_output(ec, entry): + add_pll_clock_output(bel, ec, entry) else: extra_cell_config[bel].append(entry) -- cgit v1.2.3 From 69233385f875d01a36e36924d3099175e7544b4e Mon Sep 17 00:00:00 2001 From: Sergiusz Bazanski Date: Mon, 23 Jul 2018 21:49:02 +0100 Subject: ice40: Emit feed-through LUTs for PLL/LOCK --- ice40/chipdb.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'ice40/chipdb.py') diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 63f08e36..602477a0 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -617,7 +617,7 @@ def add_pll_clock_output(bel, ec, ec_entry): } wire_downhill_belports[wire_idx] = {(bel, port),} - bel_wires[bel].append((wire_idx, port)) + bel_wires[bel].append((wire_idx, port, beltypes['PLL'])) io_wire = wire_names[(io_x, io_y, 'io_{}/D_IN_0'.format(io_z))] wire_downhill[wire_idx] = {io_wire,} -- cgit v1.2.3 From 65ceb20784ccd0e2be71c733dbc23dc61d83d653 Mon Sep 17 00:00:00 2001 From: Sergiusz Bazanski Date: Tue, 24 Jul 2018 02:05:30 +0100 Subject: ice40: emit list of upbels in chipdb --- ice40/chipdb.py | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) (limited to 'ice40/chipdb.py') diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 602477a0..38989a0b 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -41,7 +41,7 @@ extra_cells = dict() extra_cell_config = dict() packages = list() -wire_uphill_belport = dict() +wire_uphill_belports = dict() wire_downhill_belports = dict() wire_belports = dict() @@ -462,8 +462,9 @@ def add_bel_input(bel, wire, port): bel_wires[bel].append((wire, port, 0)) def add_bel_output(bel, wire, port): - assert wire not in wire_uphill_belport - wire_uphill_belport[wire] = (bel, port) + if wire not in wire_uphill_belports: + wire_uphill_belports[wire] = set() + wire_uphill_belports[wire].add((bel, port)) if wire not in wire_belports: wire_belports[wire] = set() wire_belports[wire].add((bel, port)) @@ -1042,6 +1043,15 @@ for wire in range(num_wires): num_downhill = 0 list_downhill = None + if wire in wire_uphill_belports: + num_bels_uphill = len(wire_uphill_belports[wire]) + bba.l("wire%d_upbels" % wire, "BelPortPOD") + for belport in sorted(wire_uphill_belports[wire]): + bba.u32(belport[0], "bel_index") + bba.u32(portpins[belport[1]], "port") + else: + num_bels_uphill = 0 + if wire in wire_downhill_belports: num_bels_downhill = len(wire_downhill_belports[wire]) bba.l("wire%d_downbels" % wire, "BelPortPOD") @@ -1072,16 +1082,12 @@ for wire in range(num_wires): info["num_bels_downhill"] = num_bels_downhill info["list_bels_downhill"] = ("wire%d_downbels" % wire) if num_bels_downhill > 0 else None + info["num_bels_uphill"] = num_bels_uphill + info["list_bels_uphill"] = ("wire%d_upbels" % wire) if num_bels_uphill > 0 else None + info["num_bel_pins"] = num_bel_pins info["list_bel_pins"] = ("wire%d_bels" % wire) if num_bel_pins > 0 else None - if wire in wire_uphill_belport: - info["uphill_bel"] = wire_uphill_belport[wire][0] - info["uphill_pin"] = portpins[wire_uphill_belport[wire][1]] - else: - info["uphill_bel"] = -1 - info["uphill_pin"] = 0 - avg_x, avg_y = 0, 0 if wire in wire_xy: for x, y in wire_xy[wire]: @@ -1156,9 +1162,9 @@ for wire, info in enumerate(wireinfo): bba.u32(info["num_downhill"], "num_downhill") bba.r(info["list_uphill"], "pips_uphill") bba.r(info["list_downhill"], "pips_downhill") + bba.u32(info["num_bels_uphill"], "num_bels_uphill") bba.u32(info["num_bels_downhill"], "num_bels_downhill") - bba.u32(info["uphill_bel"], "bel_uphill.bel_index") - bba.u32(info["uphill_pin"], "bel_uphill.port") + bba.r(info["list_bels_uphill"], "bels_uphill") bba.r(info["list_bels_downhill"], "bels_downhill") bba.u32(info["num_bel_pins"], "num_bel_pins") bba.r(info["list_bel_pins"], "bel_pins") -- cgit v1.2.3 From eaae1d299c030be85aa9eb3a45ce2c02afe919f1 Mon Sep 17 00:00:00 2001 From: Sergiusz Bazanski Date: Tue, 24 Jul 2018 02:35:16 +0100 Subject: ice40: move PLL->IO from pseudo pip to second uphill bel --- ice40/chipdb.py | 38 +++----------------------------------- 1 file changed, 3 insertions(+), 35 deletions(-) (limited to 'ice40/chipdb.py') diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 38989a0b..63d90b45 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -597,40 +597,6 @@ def is_ec_output(ec_entry): def is_ec_pll_clock_output(ec, ec_entry): return ec[0] == 'PLL' and ec_entry[0] in ('PLLOUT_A', 'PLLOUT_B') -def add_pll_clock_output(bel, ec, ec_entry): - #print('add_pll_clock_output', ec, ec_entry) - pll_x, pll_y, pll_z = ec[1], ec[2], ec[3] - port = ec_entry[0] - io_x, io_y, io_z = ec_entry[1] - io_z = int(io_z) - - global num_wires - wire_idx = num_wires - num_wires = num_wires + 1 - - wire_xy[wire_idx] = [(pll_x, pll_y)] - - wire_names_r[wire_idx] = (pll_x, pll_y, port) - wire_names[(pll_x, pll_y, port)] = wire_idx - wire_segments[wire_idx] = { - (pll_x, pll_y): port, - (io_x, io_y): 'PLLIN', - } - - wire_downhill_belports[wire_idx] = {(bel, port),} - bel_wires[bel].append((wire_idx, port, beltypes['PLL'])) - - io_wire = wire_names[(io_x, io_y, 'io_{}/D_IN_0'.format(io_z))] - wire_downhill[wire_idx] = {io_wire,} - if io_wire not in wire_uphill: - wire_uphill[io_wire] = set() - wire_uphill[io_wire].add(wire_idx) - - switches.append((io_x, io_y, 0, [])) - switchnum = len(switches) - 1 - pip_xy[(wire_idx, io_wire)] = (io_x, io_y, 0, switchnum) - - def add_bel_ec(ec): ectype, x, y, z = ec bel = len(bel_name) @@ -646,7 +612,9 @@ def add_bel_ec(ec): else: add_bel_input(bel, wire_names[entry[1]], entry[0]) elif is_ec_pll_clock_output(ec, entry): - add_pll_clock_output(bel, ec, entry) + x, y, z = entry[1] + z = 'io_{}/D_IN_0'.format(z) + add_bel_output(bel, wire_names[(x, y, z)], entry[0]) else: extra_cell_config[bel].append(entry) -- cgit v1.2.3 From a09f95bb06025afecd5753c969443928f1f0894a Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 24 Jul 2018 11:16:33 +0200 Subject: ice40: Fix SPRAM and other primitives in corners other than (0, 0) Signed-off-by: David Shah --- ice40/chipdb.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'ice40/chipdb.py') diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 0e8e3ba7..4dcddbed 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -662,7 +662,7 @@ for tile_xy, tile_type in sorted(tiles.items()): add_bel_ec(ec) for ec in sorted(extra_cells.keys()): - if ec[1] == 0 and ec[2] == 0: + if ec[1] in (0, dev_width - 1) and ec[2] in (0, dev_height - 1): add_bel_ec(ec) class BinaryBlobAssembler: -- cgit v1.2.3 From c0c8dc760290cb78611f3764219a7604f6f73c44 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 24 Jul 2018 15:44:39 +0200 Subject: Remove uphill/downhill bel pins from ice40 db Signed-off-by: Clifford Wolf --- ice40/chipdb.py | 30 ------------------------------ 1 file changed, 30 deletions(-) (limited to 'ice40/chipdb.py') diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 4dcddbed..1127767d 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -41,8 +41,6 @@ extra_cells = dict() extra_cell_config = dict() packages = list() -wire_uphill_belport = dict() -wire_downhill_belports = dict() wire_belports = dict() wire_names = dict() @@ -451,17 +449,12 @@ for i in range(8): add_wire(0, 0, "padin_%d" % i) def add_bel_input(bel, wire, port): - if wire not in wire_downhill_belports: - wire_downhill_belports[wire] = set() - wire_downhill_belports[wire].add((bel, port)) if wire not in wire_belports: wire_belports[wire] = set() wire_belports[wire].add((bel, port)) bel_wires[bel].append((wire, port, 0)) def add_bel_output(bel, wire, port): - assert wire not in wire_uphill_belport - wire_uphill_belport[wire] = (bel, port) if wire not in wire_belports: wire_belports[wire] = set() wire_belports[wire].add((bel, port)) @@ -1001,15 +994,6 @@ for wire in range(num_wires): num_downhill = 0 list_downhill = None - if wire in wire_downhill_belports: - num_bels_downhill = len(wire_downhill_belports[wire]) - bba.l("wire%d_downbels" % wire, "BelPortPOD") - for belport in sorted(wire_downhill_belports[wire]): - bba.u32(belport[0], "bel_index") - bba.u32(portpins[belport[1]], "port") - else: - num_bels_downhill = 0 - if wire in wire_belports: num_bel_pins = len(wire_belports[wire]) bba.l("wire%d_bels" % wire, "BelPortPOD") @@ -1028,19 +1012,9 @@ for wire in range(num_wires): info["num_downhill"] = num_downhill info["list_downhill"] = list_downhill - info["num_bels_downhill"] = num_bels_downhill - info["list_bels_downhill"] = ("wire%d_downbels" % wire) if num_bels_downhill > 0 else None - info["num_bel_pins"] = num_bel_pins info["list_bel_pins"] = ("wire%d_bels" % wire) if num_bel_pins > 0 else None - if wire in wire_uphill_belport: - info["uphill_bel"] = wire_uphill_belport[wire][0] - info["uphill_pin"] = portpins[wire_uphill_belport[wire][1]] - else: - info["uphill_bel"] = -1 - info["uphill_pin"] = 0 - avg_x, avg_y = 0, 0 if wire in wire_xy: for x, y in wire_xy[wire]: @@ -1115,10 +1089,6 @@ for wire, info in enumerate(wireinfo): bba.u32(info["num_downhill"], "num_downhill") bba.r(info["list_uphill"], "pips_uphill") bba.r(info["list_downhill"], "pips_downhill") - bba.u32(info["num_bels_downhill"], "num_bels_downhill") - bba.u32(info["uphill_bel"], "bel_uphill.bel_index") - bba.u32(info["uphill_pin"], "bel_uphill.port") - bba.r(info["list_bels_downhill"], "bels_downhill") bba.u32(info["num_bel_pins"], "num_bel_pins") bba.r(info["list_bel_pins"], "bel_pins") bba.u32(len(wire_segments[wire]), "num_segments") -- cgit v1.2.3