From 72b4bba0e78ab962c2d70a01b4bfac2ff50a84dd Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 6 Jun 2018 16:42:42 +0200 Subject: Add ice40 geometry information Signed-off-by: Clifford Wolf --- ice40/chipdb.py | 39 +++++++++++++++++++++++++++++++-------- 1 file changed, 31 insertions(+), 8 deletions(-) (limited to 'ice40/chipdb.py') diff --git a/ice40/chipdb.py b/ice40/chipdb.py index a106b78f..58dd0dd2 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -11,15 +11,18 @@ tiles = dict() wire_uphill = dict() wire_downhill = dict() +pip_xy = dict() bel_name = list() bel_type = list() +bel_pos = list() wire_uphill_belport = dict() wire_downhill_belports = dict() wire_names = dict() wire_names_r = dict() +wire_xy = dict() def cmp_wire_names(newname, oldname): return newname < oldname @@ -45,11 +48,11 @@ with open(sys.argv[1], "r") as f: continue if line[0] == ".buffer": - mode = ("buffer", int(line[3])) + mode = ("buffer", int(line[3]), int(line[1]), int(line[2])) continue if line[0] == ".routing": - mode = ("routing", int(line[3])) + mode = ("routing", int(line[3]), int(line[1]), int(line[2])) continue if line[0] == ".io_tile": @@ -81,6 +84,9 @@ with open(sys.argv[1], "r") as f: wire_names[wname] = mode[1] if (mode[1] not in wire_names_r) or cmp_wire_names(wname, wire_names_r[mode[1]]): wire_names_r[mode[1]] = wname + if mode[1] not in wire_xy: + wire_xy[mode[1]] = list() + wire_xy[mode[1]].append((int(line[0]), int(line[1]))) continue if mode[0] == "buffer": @@ -92,6 +98,7 @@ with open(sys.argv[1], "r") as f: wire_uphill[wire_b] = set() wire_downhill[wire_a].add(wire_b) wire_uphill[wire_b].add(wire_a) + pip_xy[(wire_a, wire_b)] = (mode[2], mode[3]) continue if mode[0] == "routing": @@ -104,6 +111,7 @@ with open(sys.argv[1], "r") as f: wire_uphill[wire_b] = set() wire_downhill[wire_a].add(wire_b) wire_uphill[wire_b].add(wire_a) + pip_xy[(wire_a, wire_b)] = (mode[2], mode[3]) if wire_b not in wire_downhill: wire_downhill[wire_b] = set() @@ -111,6 +119,7 @@ with open(sys.argv[1], "r") as f: wire_uphill[wire_a] = set() wire_downhill[wire_b].add(wire_a) wire_uphill[wire_a].add(wire_b) + pip_xy[(wire_b, wire_a)] = (mode[2], mode[3]) continue def add_bel_input(bel, wire, port): @@ -126,6 +135,7 @@ def add_bel_lc(x, y, z): bel = len(bel_name) bel_name.append("%d_%d_lc%d" % (x, y, z)) bel_type.append("ICESTORM_LC") + bel_pos.append((x, y, z)) wire_cen = wire_names[(x, y, "lutff_global/cen")] wire_clk = wire_names[(x, y, "lutff_global/clk")] @@ -164,6 +174,7 @@ def add_bel_io(x, y, z): bel = len(bel_name) bel_name.append("%d_%d_lc%d" % (x, y, z)) bel_type.append("SB_IO") + bel_pos.append((x, y, z)) wire_cen = wire_names[(x, y, "io_global/cen")] wire_iclk = wire_names[(x, y, "io_global/inclk")] @@ -192,6 +203,7 @@ def add_bel_ram(x, y): bel = len(bel_name) bel_name.append("%d_%d_ram" % (x, y)) bel_type.append("ICESTORM_RAM") + bel_pos.append((x, y, 0)) if (x, y, "ram/WE") in wire_names: # iCE40 1K-style memories @@ -231,7 +243,9 @@ print('#include "chip.h"') print("BelInfoPOD bel_data_%s[%d] = {" % (dev_name, len(bel_name))) for bel in range(len(bel_name)): - print(" {\"%s\", TYPE_%s}%s" % (bel_name[bel], bel_type[bel], "," if bel+1 < len(bel_name) else "")) + print(" {\"%s\", TYPE_%s, %d, %d, %d}%s" % (bel_name[bel], bel_type[bel], + bel_pos[bel][0], bel_pos[bel][1], bel_pos[bel][2], + "," if bel+1 < len(bel_name) else "")) print("};") wireinfo = list() @@ -244,7 +258,7 @@ for wire in range(num_wires): for src in wire_uphill[wire]: if (src, wire) not in pipcache: pipcache[(src, wire)] = len(pipinfo) - pipinfo.append(" {%d, %d, 1.0}" % (src, wire)) + pipinfo.append(" {%d, %d, 1.0, %d, %d}" % (src, wire, pip_xy[(src, wire)][0], pip_xy[(src, wire)][1])) pips.append("%d" % pipcache[(src, wire)]) num_uphill = len(pips) list_uphill = "wire%d_uppips" % wire @@ -258,7 +272,7 @@ for wire in range(num_wires): for dst in wire_downhill[wire]: if (wire, dst) not in pipcache: pipcache[(wire, dst)] = len(pipinfo) - pipinfo.append(" {%d, %d, 1.0}" % (wire, dst)) + pipinfo.append(" {%d, %d, 1.0, %d, %d}" % (wire, dst, pip_xy[(wire, dst)][0], pip_xy[(wire, dst)][1])) pips.append("%d" % pipcache[(wire, dst)]) num_downhill = len(pips) list_downhill = "wire%d_downpips" % wire @@ -284,8 +298,17 @@ for wire in range(num_wires): else: info += "{-1, PIN_NIL}, " - info += ("wire%d_downbels" % wire) if num_bels_downhill > 0 else "nullptr" - info += "}" + info += ("wire%d_downbels, " % wire) if num_bels_downhill > 0 else "nullptr, " + + avg_x, avg_y = 0, 0 + if wire in wire_xy: + for x, y in wire_xy[wire]: + avg_x += x + avg_y += y + avg_x /= len(wire_xy[wire]) + avg_y /= len(wire_xy[wire]) + + info += "%f, %f}" % (avg_x, avg_y) wireinfo.append(info) @@ -298,6 +321,6 @@ print(",\n".join(pipinfo)) print("};") print("ChipInfoPOD chip_info_%s = {" % dev_name) -print(" %d, %d, %d," % (len(bel_name), num_wires, len(pipinfo))) +print(" %d, %d, %d, %d, %d," % (dev_width, dev_height, len(bel_name), num_wires, len(pipinfo))) print(" bel_data_%s, wire_data_%s, pip_data_%s" % (dev_name, dev_name, dev_name)) print("};") -- cgit v1.2.3