From 23b1fc02fb8e6bde8d9f1c444c8eb357d2301774 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 15 Jun 2018 21:29:15 +0200 Subject: ice40: Bitstream generation for RAM Signed-off-by: David Shah --- ice40/bitstream.cc | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) (limited to 'ice40/bitstream.cc') diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 7952a8a1..152d8eed 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -198,11 +198,37 @@ void write_asc(const Design &design, std::ostream &out) } } else if (cell.second->type == "SB_GB") { // no cell config bits + } else if (cell.second->type == "ICESTORM_RAM") { + const BelInfoPOD &beli = ci.bel_data[bel.index]; + int x = beli.x, y = beli.y; + const TileInfoPOD &ti_ramt = bi.tiles_nonrouting[TILE_RAMT]; + const TileInfoPOD &ti_ramb = bi.tiles_nonrouting[TILE_RAMB]; + if (!(chip.args.type == ChipArgs::LP1K || + chip.args.type == ChipArgs::HX1K)) { + set_config(ti_ramb, config.at(y).at(x), "RamConfig.PowerUp", + true); + } + bool negclk_r = std::stoi(cell.second->params.at("NEG_CLK_R")); + bool negclk_w = std::stoi(cell.second->params.at("NEG_CLK_W")); + int write_mode = std::stoi(cell.second->params.at("WRITE_MODE")); + int read_mode = std::stoi(cell.second->params.at("READ_MODE")); + set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w); + set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r); + + set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_0", + write_mode & 0x1); + set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_1", + write_mode & 0x2); + set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_2", + read_mode & 0x1); + set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_3", + read_mode & 0x2); + } else { assert(false); } } - // Set config bits in unused IO + // Set config bits in unused IO and RAM for (auto bel : chip.getBels()) { if (chip.bel_to_cell[bel.index] == IdString() && chip.getBelType(bel) == TYPE_SB_IO) { @@ -221,6 +247,15 @@ void write_asc(const Design &design, std::ostream &out) "IoCtrl.REN_" + std::to_string(iez), false); } } + } else if (chip.bel_to_cell[bel.index] == IdString() && + chip.getBelType(bel) == TYPE_ICESTORM_RAM) { + const BelInfoPOD &beli = ci.bel_data[bel.index]; + int x = beli.x, y = beli.y; + TileInfoPOD &ti = bi.tiles_nonrouting[TILE_RAMB]; + if ((chip.args.type == ChipArgs::LP1K || + chip.args.type == ChipArgs::HX1K)) { + set_config(ti, config.at(y).at(x), "RamConfig.PowerUp", true); + } } } -- cgit v1.2.3 From 04f1d7516a2001087101430c0561e31a448e0893 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 15 Jun 2018 22:08:30 +0200 Subject: ice40: Fix bitstream generation when parameters are unspecified Signed-off-by: David Shah --- ice40/bitstream.cc | 36 +++++++++++++++++++++++------------- 1 file changed, 23 insertions(+), 13 deletions(-) (limited to 'ice40/bitstream.cc') diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 152d8eed..0790a919 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -67,6 +67,16 @@ void set_config(const TileInfoPOD &ti, } } +int get_param_or_def(const CellInfo *cell, const std::string ¶m, + int defval = 0) +{ + auto found = cell->params.find(param); + if (found != cell->params.end()) + return std::stoi(found->second); + else + return defval; +} + void write_asc(const Design &design, std::ostream &out) { const Chip &chip = design.chip; @@ -134,12 +144,12 @@ void write_asc(const Design &design, std::ostream &out) int x = beli.x, y = beli.y, z = beli.z; if (cell.second->type == "ICESTORM_LC") { TileInfoPOD &ti = bi.tiles_nonrouting[TILE_LOGIC]; - unsigned lut_init = std::stoi(cell.second->params["LUT_INIT"]); - bool neg_clk = std::stoi(cell.second->params["NEG_CLK"]); - bool dff_enable = std::stoi(cell.second->params["DFF_ENABLE"]); - bool async_sr = std::stoi(cell.second->params["ASYNC_SR"]); - bool set_noreset = std::stoi(cell.second->params["SET_NORESET"]); - bool carry_enable = std::stoi(cell.second->params["CARRY_ENABLE"]); + unsigned lut_init = get_param_or_def(cell.second, "LUT_INIT"); + bool neg_clk = get_param_or_def(cell.second, "NEG_CLK"); + bool dff_enable = get_param_or_def(cell.second, "DFF_ENABLE"); + bool async_sr = get_param_or_def(cell.second, "ASYNC_SR"); + bool set_noreset = get_param_or_def(cell.second, "SET_NORESET"); + bool carry_enable = get_param_or_def(cell.second, "CARRY_ENABLE"); std::vector lc(20, false); // From arachne-pnr static std::vector lut_perm = { @@ -160,9 +170,9 @@ void write_asc(const Design &design, std::ostream &out) set_config(ti, config.at(y).at(x), "NegClk", neg_clk); } else if (cell.second->type == "SB_IO") { TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO]; - unsigned pin_type = std::stoi(cell.second->params["PIN_TYPE"]); - bool neg_trigger = std::stoi(cell.second->params["NEG_TRIGGER"]); - bool pullup = std::stoi(cell.second->params["PULLUP"]); + unsigned pin_type = get_param_or_def(cell.second, "PIN_TYPE"); + bool neg_trigger = get_param_or_def(cell.second, "NEG_TRIGGER"); + bool pullup = get_param_or_def(cell.second, "PULLUP"); for (int i = 0; i < 6; i++) { bool val = (pin_type >> i) & 0x01; set_config(ti, config.at(y).at(x), @@ -208,10 +218,10 @@ void write_asc(const Design &design, std::ostream &out) set_config(ti_ramb, config.at(y).at(x), "RamConfig.PowerUp", true); } - bool negclk_r = std::stoi(cell.second->params.at("NEG_CLK_R")); - bool negclk_w = std::stoi(cell.second->params.at("NEG_CLK_W")); - int write_mode = std::stoi(cell.second->params.at("WRITE_MODE")); - int read_mode = std::stoi(cell.second->params.at("READ_MODE")); + bool negclk_r = get_param_or_def(cell.second, "NEG_CLK_R"); + bool negclk_w = get_param_or_def(cell.second, "NEG_CLK_W"); + int write_mode = get_param_or_def(cell.second, "WRITE_MODE"); + int read_mode = get_param_or_def(cell.second, "READ_MODE"); set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w); set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r); -- cgit v1.2.3 From c9a784ec0cca9d1d39386e1e3c3dc5ec0da9c03e Mon Sep 17 00:00:00 2001 From: David Shah Date: Sat, 16 Jun 2018 11:17:17 +0200 Subject: ice40: Include RAM init data in bitstream Signed-off-by: David Shah --- ice40/bitstream.cc | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'ice40/bitstream.cc') diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 0790a919..fa8e444d 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -77,6 +77,18 @@ int get_param_or_def(const CellInfo *cell, const std::string ¶m, return defval; } +std::string get_param_str_or_def(const CellInfo *cell, const std::string ¶m, + std::string defval = "") +{ + auto found = cell->params.find(param); + if (found != cell->params.end()) + return found->second; + else + return defval; +} + +char get_hexdigit(int i) { return std::string("0123456789ABCDEF").at(i); } + void write_asc(const Design &design, std::ostream &out) { const Chip &chip = design.chip; @@ -357,6 +369,34 @@ void write_asc(const Design &design, std::ostream &out) out << std::endl; } } + + // Write RAM init data + for (auto cell : design.cells) { + if (cell.second->bel != BelId()) { + if (cell.second->type == "ICESTORM_RAM") { + const BelInfoPOD &beli = ci.bel_data[cell.second->bel.index]; + int x = beli.x, y = beli.y; + out << ".ram_data " << x << " " << y << std::endl; + for (int w = 0; w < 16; w++) { + std::vector bits(256); + std::string init = get_param_str_or_def( + cell.second, + std::string("INIT_") + get_hexdigit(w)); + for (int i = 0; i < init.size(); i++) { + bool val = (init.at((init.size() - 1) - i) == '1'); + bits.at(i) = val; + } + for (int i = 0; i < bits.size(); i += 4) { + int c = bits.at(i) + (bits.at(i + 1) << 1) + + (bits.at(i + 2) << 2) + (bits.at(i + 3) << 3); + out << get_hexdigit(c); + } + out << std::endl; + } + out << std::endl; + } + } + } } NEXTPNR_NAMESPACE_END -- cgit v1.2.3 From f079e0d204117b53a91da2805d31136607a5ca0e Mon Sep 17 00:00:00 2001 From: David Shah Date: Sat, 16 Jun 2018 12:17:36 +0200 Subject: ice40: Fix BRAM initialisation Signed-off-by: David Shah --- ice40/bitstream.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'ice40/bitstream.cc') diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index fa8e444d..ba4a0e8d 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -382,14 +382,15 @@ void write_asc(const Design &design, std::ostream &out) std::string init = get_param_str_or_def( cell.second, std::string("INIT_") + get_hexdigit(w)); + assert(init != ""); for (int i = 0; i < init.size(); i++) { bool val = (init.at((init.size() - 1) - i) == '1'); bits.at(i) = val; } - for (int i = 0; i < bits.size(); i += 4) { + for (int i = bits.size()-4; i >= 0; i -= 4) { int c = bits.at(i) + (bits.at(i + 1) << 1) + (bits.at(i + 2) << 2) + (bits.at(i + 3) << 3); - out << get_hexdigit(c); + out << char(std::tolower(get_hexdigit(c))); } out << std::endl; } -- cgit v1.2.3