From 428f0b9ebaec7bd0cf86ecbc50d1edd3a7bf0c51 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 14 Aug 2018 17:16:14 +0200 Subject: Add Arch attrs API Signed-off-by: Clifford Wolf --- ice40/arch.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'ice40/arch.h') diff --git a/ice40/arch.h b/ice40/arch.h index 8fd1af23..b955a478 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -502,6 +502,12 @@ struct Arch : BaseCtx return IdString(chip_info->bel_data[bel.index].type); } + std::vector> getBelAttrs(BelId) const + { + std::vector> ret; + return ret; + } + WireId getBelPinWire(BelId bel, IdString pin) const; PortType getBelPinType(BelId bel, IdString pin) const; std::vector getBelPins(BelId bel) const; @@ -518,6 +524,12 @@ struct Arch : BaseCtx IdString getWireType(WireId wire) const; + std::vector> getWireAttrs(WireId) const + { + std::vector> ret; + return ret; + } + uint32_t getWireChecksum(WireId wire) const { return wire.index; } void bindWire(WireId wire, NetInfo *net, PlaceStrength strength) @@ -694,6 +706,12 @@ struct Arch : BaseCtx IdString getPipType(PipId pip) const { return IdString(); } + std::vector> getPipAttrs(PipId) const + { + std::vector> ret; + return ret; + } + uint32_t getPipChecksum(PipId pip) const { return pip.index; } WireId getPipSrcWire(PipId pip) const -- cgit v1.2.3 From 5500cf3aff5daa4d094c7c4ab46551105f0cb7cc Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 18 Aug 2018 14:14:27 +0200 Subject: Add ice40 wire attributes (grid position, segment list) Signed-off-by: Clifford Wolf --- ice40/arch.h | 23 +++++------------------ 1 file changed, 5 insertions(+), 18 deletions(-) (limited to 'ice40/arch.h') diff --git a/ice40/arch.h b/ice40/arch.h index b955a478..efdcc188 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -225,6 +225,7 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD { RelPtr bel_config; RelPtr packages_data; RelPtr cell_timing; + RelPtr> tile_wire_names; }); #if defined(_MSC_VER) @@ -502,11 +503,7 @@ struct Arch : BaseCtx return IdString(chip_info->bel_data[bel.index].type); } - std::vector> getBelAttrs(BelId) const - { - std::vector> ret; - return ret; - } + std::vector> getBelAttrs(BelId bel) const; WireId getBelPinWire(BelId bel, IdString pin) const; PortType getBelPinType(BelId bel, IdString pin) const; @@ -523,12 +520,7 @@ struct Arch : BaseCtx } IdString getWireType(WireId wire) const; - - std::vector> getWireAttrs(WireId) const - { - std::vector> ret; - return ret; - } + std::vector> getWireAttrs(WireId wire) const; uint32_t getWireChecksum(WireId wire) const { return wire.index; } @@ -704,13 +696,8 @@ struct Arch : BaseCtx IdString getPipName(PipId pip) const; - IdString getPipType(PipId pip) const { return IdString(); } - - std::vector> getPipAttrs(PipId) const - { - std::vector> ret; - return ret; - } + IdString getPipType(PipId pip) const; + std::vector> getPipAttrs(PipId pip) const; uint32_t getPipChecksum(PipId pip) const { return pip.index; } -- cgit v1.2.3 From 456a83430ac85c23045f95d3fe0c6d380413fe92 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 18 Aug 2018 16:20:33 +0200 Subject: Improve iCE40 gfx for IO tiles and RAM tiles Signed-off-by: Clifford Wolf --- ice40/arch.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'ice40/arch.h') diff --git a/ice40/arch.h b/ice40/arch.h index efdcc188..7f61c376 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -108,6 +108,8 @@ NPNR_PACKED_STRUCT(struct WireInfoPOD { }; RelPtr name; + int32_t netidx; + int32_t num_uphill, num_downhill; RelPtr pips_uphill, pips_downhill; -- cgit v1.2.3