From e633aa09ccd89040d450b7cb4b7864c4fd8c0468 Mon Sep 17 00:00:00 2001 From: David Shah Date: Sat, 3 Nov 2018 14:09:27 +0000 Subject: timing: Fix handling of clock inputs Signed-off-by: David Shah --- ice40/arch.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'ice40/arch.cc') diff --git a/ice40/arch.cc b/ice40/arch.cc index c14fecc4..2d910d6f 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -894,7 +894,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in else return TMG_REGISTER_INPUT; } else if (cell->type == id_ICESTORM_DSP || cell->type == id_ICESTORM_SPRAM) { - if (port == id_CLK) + if (port == id_CLK || port == id_CLOCK) return TMG_CLOCK_INPUT; else { clockInfoCount = 1; @@ -960,7 +960,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port info.hold.delay = 0; } } else if (cell->type == id_ICESTORM_DSP || cell->type == id_ICESTORM_SPRAM) { - info.clock_port = id_CLK; + info.clock_port = cell->type == id_ICESTORM_SPRAM ? id_CLOCK : id_CLK; info.edge = RISING_EDGE; if (cell->ports.at(port).type == PORT_OUT) { bool has_clktoq = getCellDelay(cell, info.clock_port, port, info.clockToQ); -- cgit v1.2.3