From c10238de8c6087282ff1d6092929585277cbd17c Mon Sep 17 00:00:00 2001
From: "D. Shah" <dave@ds0.me>
Date: Wed, 27 Jan 2021 18:34:41 +0000
Subject: ice40: Switch from RelPtr to RelSlice

This replaces RelPtrs and a separate length field with a Rust-style
slice containing both a pointer and a length; with bounds checking
always enforced.

Thus iterating over these structures is both cleaner and safer.

Signed-off-by: D. Shah <dave@ds0.me>
---
 gui/designwidget.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'gui')

diff --git a/gui/designwidget.cc b/gui/designwidget.cc
index 457b7de4..f856b5f6 100644
--- a/gui/designwidget.cc
+++ b/gui/designwidget.cc
@@ -306,7 +306,7 @@ void DesignWidget::newContext(Context *ctx)
         {
             TreeModel::ElementXYRoot<WireId>::ElementMap wireMap;
 #ifdef ARCH_ICE40
-            for (int i = 0; i < ctx->chip_info->num_wires; i++) {
+            for (int i = 0; i < int(ctx->chip_info->wire_data.size()); i++) {
                 const auto wire = &ctx->chip_info->wire_data[i];
                 WireId wireid;
                 wireid.index = i;
-- 
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