From 590b9050ff5cc618b4df50e0877b4bf6d9e7949d Mon Sep 17 00:00:00 2001 From: YRabbit Date: Thu, 23 Jun 2022 11:42:58 +1000 Subject: gowin: add a separate router for the clocks A simple router that takes advantage of the fact that in each cell with DFFs their CLK inputs can directly connect to the global clock network. Networks with a large number of such sinks are sought and then each network is assigned to the available independent global clock networks. There are limited possibilities for routing mixed networks, that is, when the sinks are not only CLKs: in this case an attempt is made to use wires such as SN10/20 and EW10/20, that is, one short transition can be added between the global clock network and the sink. * At this time, networks with a source other than the I/O pin are not supported. This is typical for Tangnano4k and runber boards. * Router is disabled by default, you need to specify option --enable-globals to activate * No new chip bases are required. This may change in the distant future. Signed-off-by: YRabbit --- gowin/arch.h | 1 + 1 file changed, 1 insertion(+) (limited to 'gowin/arch.h') diff --git a/gowin/arch.h b/gowin/arch.h index 8bbbd514..c59f8eb3 100644 --- a/gowin/arch.h +++ b/gowin/arch.h @@ -289,6 +289,7 @@ struct Arch : BaseArch WireInfo &wire_info(IdString wire); PipInfo &pip_info(IdString pip); BelInfo &bel_info(IdString bel); + NetInfo &net_info(IdString net); std::vector bel_ids, wire_ids, pip_ids; -- cgit v1.2.3