From ecc19c2c083f7e3ed7da95557731ded803d2cb1d Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 2 Jun 2021 10:01:36 +0100
Subject: Using hashlib in arches

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/arch.h     | 39 +++++++++++++--------------------------
 generic/archdefs.h |  5 ++---
 generic/cells.cc   |  2 +-
 generic/cells.h    |  2 +-
 generic/pack.cc    |  9 ++++-----
 5 files changed, 21 insertions(+), 36 deletions(-)

(limited to 'generic')

diff --git a/generic/arch.h b/generic/arch.h
index 50d2731c..9b16d873 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -80,7 +80,7 @@ struct BelInfo
     IdString type;
     std::map<IdString, std::string> attrs;
     CellInfo *bound_cell;
-    std::unordered_map<IdString, PinInfo> pins;
+    dict<IdString, PinInfo> pins;
     DecalXY decalxy;
     int x, y, z;
     bool gb;
@@ -101,27 +101,14 @@ struct CellDelayKey
 {
     IdString from, to;
     inline bool operator==(const CellDelayKey &other) const { return from == other.from && to == other.to; }
+    unsigned int hash() const { return mkhash(from.hash(), to.hash()); }
 };
 
-NEXTPNR_NAMESPACE_END
-namespace std {
-template <> struct hash<NEXTPNR_NAMESPACE_PREFIX CellDelayKey>
-{
-    std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX CellDelayKey &dk) const noexcept
-    {
-        std::size_t seed = std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(dk.from);
-        seed ^= std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(dk.to) + 0x9e3779b9 + (seed << 6) + (seed >> 2);
-        return seed;
-    }
-};
-} // namespace std
-NEXTPNR_NAMESPACE_BEGIN
-
 struct CellTiming
 {
-    std::unordered_map<IdString, TimingPortClass> portClasses;
-    std::unordered_map<CellDelayKey, DelayQuad> combDelays;
-    std::unordered_map<IdString, std::vector<TimingClockingInfo>> clockingInfo;
+    dict<IdString, TimingPortClass> portClasses;
+    dict<CellDelayKey, DelayQuad> combDelays;
+    dict<IdString, std::vector<TimingClockingInfo>> clockingInfo;
 };
 
 struct ArchRanges
@@ -160,10 +147,10 @@ struct Arch : ArchAPI<ArchRanges>
 {
     std::string chipName;
 
-    std::unordered_map<IdStringList, WireInfo> wires;
-    std::unordered_map<IdStringList, PipInfo> pips;
-    std::unordered_map<IdStringList, BelInfo> bels;
-    std::unordered_map<GroupId, GroupInfo> groups;
+    dict<IdStringList, WireInfo> wires;
+    dict<IdStringList, PipInfo> pips;
+    dict<IdStringList, BelInfo> bels;
+    dict<GroupId, GroupInfo> groups;
 
     // These functions include useful errors if not found
     WireInfo &wire_info(IdStringList wire);
@@ -172,16 +159,16 @@ struct Arch : ArchAPI<ArchRanges>
 
     std::vector<IdStringList> bel_ids, wire_ids, pip_ids;
 
-    std::unordered_map<Loc, BelId> bel_by_loc;
+    dict<Loc, BelId> bel_by_loc;
     std::vector<std::vector<std::vector<BelId>>> bels_by_tile;
 
-    std::unordered_map<DecalId, std::vector<GraphicElement>> decal_graphics;
+    dict<DecalId, std::vector<GraphicElement>> decal_graphics;
 
     int gridDimX, gridDimY;
     std::vector<std::vector<int>> tileBelDimZ;
     std::vector<std::vector<int>> tilePipDimZ;
 
-    std::unordered_map<IdString, CellTiming> cellTiming;
+    dict<IdString, CellTiming> cellTiming;
 
     void addWire(IdStringList name, IdString type, int x, int y);
     void addPip(IdStringList name, IdString type, IdStringList srcWire, IdStringList dstWire, delay_t delay, Loc loc);
@@ -318,7 +305,7 @@ struct Arch : ArchAPI<ArchRanges>
 
     std::vector<IdString> getCellTypes() const override
     {
-        std::unordered_set<IdString> cell_types;
+        pool<IdString> cell_types;
         for (auto bel : bels) {
             cell_types.insert(bel.second.type);
         }
diff --git a/generic/archdefs.h b/generic/archdefs.h
index 0489ab04..06680cc1 100644
--- a/generic/archdefs.h
+++ b/generic/archdefs.h
@@ -20,8 +20,7 @@
 #ifndef GENERIC_ARCHDEFS_H
 #define GENERIC_ARCHDEFS_H
 
-#include <unordered_map>
-
+#include "hashlib.h"
 #include "idstringlist.h"
 
 NEXTPNR_NAMESPACE_BEGIN
@@ -52,7 +51,7 @@ struct ArchCellInfo
     // Only packing rule for slice type primitives is a single clock per tile
     const NetInfo *slice_clk;
     // Cell to bel pin mapping
-    std::unordered_map<IdString, std::vector<IdString>> bel_pins;
+    dict<IdString, std::vector<IdString>> bel_pins;
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/generic/cells.cc b/generic/cells.cc
index c4421f90..e1892353 100644
--- a/generic/cells.cc
+++ b/generic/cells.cc
@@ -106,7 +106,7 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
     replace_port(dff, ctx->id("Q"), lc, ctx->id("Q"));
 }
 
-void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, std::unordered_set<IdString> &todelete_cells)
+void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, pool<IdString> &todelete_cells)
 {
     if (nxio->type == ctx->id("$nextpnr_ibuf")) {
         iob->params[ctx->id("INPUT_USED")] = 1;
diff --git a/generic/cells.h b/generic/cells.h
index 646d738d..7a8443c5 100644
--- a/generic/cells.h
+++ b/generic/cells.h
@@ -48,7 +48,7 @@ void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff = tr
 void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_lut = false);
 
 // Convert a nextpnr IO buffer to a GENERIC_IOB
-void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *sbio, std::unordered_set<IdString> &todelete_cells);
+void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &todelete_cells);
 
 NEXTPNR_NAMESPACE_END
 
diff --git a/generic/pack.cc b/generic/pack.cc
index a1c325f8..dba86cce 100644
--- a/generic/pack.cc
+++ b/generic/pack.cc
@@ -19,7 +19,6 @@
 
 #include <algorithm>
 #include <iterator>
-#include <unordered_set>
 #include "cells.h"
 #include "design_utils.h"
 #include "log.h"
@@ -32,7 +31,7 @@ static void pack_lut_lutffs(Context *ctx)
 {
     log_info("Packing LUT-FFs..\n");
 
-    std::unordered_set<IdString> packed_cells;
+    pool<IdString> packed_cells;
     std::vector<std::unique_ptr<CellInfo>> new_cells;
     for (auto &cell : ctx->cells) {
         CellInfo *ci = cell.second.get();
@@ -89,7 +88,7 @@ static void pack_nonlut_ffs(Context *ctx)
 {
     log_info("Packing non-LUT FFs..\n");
 
-    std::unordered_set<IdString> packed_cells;
+    pool<IdString> packed_cells;
     std::vector<std::unique_ptr<CellInfo>> new_cells;
 
     for (auto &cell : ctx->cells) {
@@ -203,8 +202,8 @@ static bool is_generic_iob(const Context *ctx, const CellInfo *cell) { return ce
 // Pack IO buffers
 static void pack_io(Context *ctx)
 {
-    std::unordered_set<IdString> packed_cells;
-    std::unordered_set<IdString> delete_nets;
+    pool<IdString> packed_cells;
+    pool<IdString> delete_nets;
 
     std::vector<std::unique_ptr<CellInfo>> new_cells;
     log_info("Packing IOs..\n");
-- 
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