From ebcdfc1ae83eaef8e4a4d7586385eafdf8443386 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 5 Aug 2019 17:28:54 +0100 Subject: generic: New Property interface Signed-off-by: David Shah --- generic/arch.cc | 4 ++-- generic/cells.cc | 26 +++++++++++++------------- generic/examples/simple_timing.py | 2 +- generic/examples/write_fasm.py | 3 +-- generic/main.cc | 2 +- generic/pack.cc | 6 +++--- 6 files changed, 21 insertions(+), 22 deletions(-) (limited to 'generic') diff --git a/generic/arch.cc b/generic/arch.cc index fa3c825d..9e59540e 100644 --- a/generic/arch.cc +++ b/generic/arch.cc @@ -497,7 +497,7 @@ bool Arch::place() // FIXME: No HeAP because it needs a list of IO buffers if (placer == "sa") { bool retVal = placer1(getCtx(), Placer1Cfg(getCtx())); - getCtx()->settings[getCtx()->id("place")] = "1"; + getCtx()->settings[getCtx()->id("place")] = 1; archInfoToAttributes(); return retVal; } else { @@ -508,7 +508,7 @@ bool Arch::place() bool Arch::route() { bool retVal = router1(getCtx(), Router1Cfg(getCtx())); - getCtx()->settings[getCtx()->id("route")] = "1"; + getCtx()->settings[getCtx()->id("route")] = 1; archInfoToAttributes(); return retVal; } diff --git a/generic/cells.cc b/generic/cells.cc index 14b368b2..53886e33 100644 --- a/generic/cells.cc +++ b/generic/cells.cc @@ -43,8 +43,8 @@ std::unique_ptr create_generic_cell(Context *ctx, IdString type, std:: new_cell->type = type; if (type == ctx->id("GENERIC_SLICE")) { new_cell->params[ctx->id("K")] = std::to_string(ctx->args.K); - new_cell->params[ctx->id("INIT")] = "0"; - new_cell->params[ctx->id("FF_USED")] = "0"; + new_cell->params[ctx->id("INIT")] = 0; + new_cell->params[ctx->id("FF_USED")] = 0; for (int i = 0; i < ctx->args.K; i++) add_port(ctx, new_cell.get(), "I[" + std::to_string(i) + "]", PORT_IN); @@ -53,9 +53,9 @@ std::unique_ptr create_generic_cell(Context *ctx, IdString type, std:: add_port(ctx, new_cell.get(), "Q", PORT_OUT); } else if (type == ctx->id("GENERIC_IOB")) { - new_cell->params[ctx->id("INPUT_USED")] = "0"; - new_cell->params[ctx->id("OUTPUT_USED")] = "0"; - new_cell->params[ctx->id("ENABLE_USED")] = "0"; + new_cell->params[ctx->id("INPUT_USED")] = 0; + new_cell->params[ctx->id("OUTPUT_USED")] = 0; + new_cell->params[ctx->id("ENABLE_USED")] = 0; add_port(ctx, new_cell.get(), "PAD", PORT_INOUT); add_port(ctx, new_cell.get(), "I", PORT_IN); @@ -81,17 +81,17 @@ void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff) if (no_dff) { replace_port(lut, ctx->id("Q"), lc, ctx->id("Q")); - lc->params[ctx->id("FF_USED")] = "0"; + lc->params[ctx->id("FF_USED")] = 0; } } void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_lut) { - lc->params[ctx->id("FF_USED")] = "1"; + lc->params[ctx->id("FF_USED")] = 1; replace_port(dff, ctx->id("CLK"), lc, ctx->id("CLK")); if (pass_thru_lut) { - lc->params[ctx->id("INIT")] = "2"; + lc->params[ctx->id("INIT")] = 2; replace_port(dff, ctx->id("D"), lc, ctx->id("I[0]")); } @@ -101,15 +101,15 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, std::unordered_set &todelete_cells) { if (nxio->type == ctx->id("$nextpnr_ibuf")) { - iob->params[ctx->id("INPUT_USED")] = "1"; + iob->params[ctx->id("INPUT_USED")] = 1; replace_port(nxio, ctx->id("O"), iob, ctx->id("O")); } else if (nxio->type == ctx->id("$nextpnr_obuf")) { - iob->params[ctx->id("OUTPUT_USED")] = "1"; + iob->params[ctx->id("OUTPUT_USED")] = 1; replace_port(nxio, ctx->id("I"), iob, ctx->id("I")); } else if (nxio->type == ctx->id("$nextpnr_iobuf")) { // N.B. tristate will be dealt with below - iob->params[ctx->id("INPUT_USED")] = "1"; - iob->params[ctx->id("OUTPUT_USED")] = "1"; + iob->params[ctx->id("INPUT_USED")] = 1; + iob->params[ctx->id("OUTPUT_USED")] = 1; replace_port(nxio, ctx->id("I"), iob, ctx->id("I")); replace_port(nxio, ctx->id("O"), iob, ctx->id("O")); } else { @@ -120,7 +120,7 @@ void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, std::unordered_set ctx, donet, [](const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("$_TBUF_"); }, ctx->id("Y")); if (tbuf) { - iob->params[ctx->id("ENABLE_USED")] = "1"; + iob->params[ctx->id("ENABLE_USED")] = 1; replace_port(tbuf, ctx->id("A"), iob, ctx->id("I")); replace_port(tbuf, ctx->id("E"), iob, ctx->id("EN")); diff --git a/generic/examples/simple_timing.py b/generic/examples/simple_timing.py index a955c8d7..2ccb197e 100644 --- a/generic/examples/simple_timing.py +++ b/generic/examples/simple_timing.py @@ -4,7 +4,7 @@ for cname, cell in ctx.cells: if cname in ("$PACKER_GND", "$PACKER_VCC"): continue K = int(cell.params["K"]) - if cell.params["FF_USED"] == "1": + if int(cell.params["FF_USED"], 2) == 1: ctx.addCellTimingClock(cell=cname, port="CLK") for i in range(K): ctx.addCellTimingSetupHold(cell=cname, port="I[%d]" % i, clock="CLK", diff --git a/generic/examples/write_fasm.py b/generic/examples/write_fasm.py index 1f279b63..ede8f16b 100644 --- a/generic/examples/write_fasm.py +++ b/generic/examples/write_fasm.py @@ -45,8 +45,7 @@ def write_fasm(ctx, paramCfg, f): print("%s.%s" % (cell.bel, fasm_name), file=f) else: # Parameters with width >32 are direct binary, otherwise denary - binval = val if cfg.width > 32 else "{:0{}b}".format(int(val), cfg.width) - print("%s.%s[%d:0] = %d'b%s" % (cell.bel, fasm_name, cfg.width-1, cfg.width, binval), file=f) + print("%s.%s[%d:0] = %d'b%s" % (cell.bel, fasm_name, cfg.width-1, cfg.width, val), file=f) else: print("%s.%s.%s" % (cell.bel, fasm_name, val), file=f) print("", file=f) \ No newline at end of file diff --git a/generic/main.cc b/generic/main.cc index ce1a51c7..7dfc6aa7 100644 --- a/generic/main.cc +++ b/generic/main.cc @@ -55,7 +55,7 @@ std::unique_ptr GenericCommandHandler::createContext(std::unordered_map { ArchArgs chipArgs; if (values.find("arch.name") != values.end()) { - std::string arch_name = values["arch.name"].str; + std::string arch_name = values["arch.name"].as_string(); if (arch_name != "generic") log_error("Unsuported architecture '%s'.\n", arch_name.c_str()); } diff --git a/generic/pack.cc b/generic/pack.cc index 558eca7c..3dc12bc1 100644 --- a/generic/pack.cc +++ b/generic/pack.cc @@ -150,7 +150,7 @@ static void pack_constants(Context *ctx) log_info("Packing constants..\n"); std::unique_ptr gnd_cell = create_generic_cell(ctx, ctx->id("GENERIC_SLICE"), "$PACKER_GND"); - gnd_cell->params[ctx->id("INIT")] = "0"; + gnd_cell->params[ctx->id("INIT")] = 0; std::unique_ptr gnd_net = std::unique_ptr(new NetInfo); gnd_net->name = ctx->id("$PACKER_GND_NET"); gnd_net->driver.cell = gnd_cell.get(); @@ -158,7 +158,7 @@ static void pack_constants(Context *ctx) gnd_cell->ports.at(ctx->id("Q")).net = gnd_net.get(); std::unique_ptr vcc_cell = create_generic_cell(ctx, ctx->id("GENERIC_SLICE"), "$PACKER_VCC"); - vcc_cell->params[ctx->id("INIT")] = "1"; + vcc_cell->params[ctx->id("INIT")] = 1; std::unique_ptr vcc_net = std::unique_ptr(new NetInfo); vcc_net->name = ctx->id("$PACKER_VCC_NET"); vcc_net->driver.cell = vcc_cell.get(); @@ -282,7 +282,7 @@ bool Arch::pack() pack_io(ctx); pack_lut_lutffs(ctx); pack_nonlut_ffs(ctx); - ctx->settings[ctx->id("pack")] = "1"; + ctx->settings[ctx->id("pack")] = 1; ctx->assignArchInfo(); log_info("Checksum: 0x%08x\n", ctx->checksum()); return true; -- cgit v1.2.3