From c4e47ba1a85d840c31d4be5c3f2c032664abd814 Mon Sep 17 00:00:00 2001 From: gatecat Date: Mon, 4 Apr 2022 19:49:44 +0100 Subject: generic: Allow bel pins without wires Signed-off-by: gatecat --- generic/arch.cc | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'generic') diff --git a/generic/arch.cc b/generic/arch.cc index c4814bab..0aece64f 100644 --- a/generic/arch.cc +++ b/generic/arch.cc @@ -119,7 +119,8 @@ void Arch::addBelInput(BelId bel, IdString name, WireId wire) pi.wire = wire; pi.type = PORT_IN; - wire_info(wire).bel_pins.push_back(BelPin{bel, name}); + if (wire != WireId()) + wire_info(wire).bel_pins.push_back(BelPin{bel, name}); } void Arch::addBelOutput(BelId bel, IdString name, WireId wire) @@ -131,7 +132,8 @@ void Arch::addBelOutput(BelId bel, IdString name, WireId wire) pi.wire = wire; pi.type = PORT_OUT; - wire_info(wire).bel_pins.push_back(BelPin{bel, name}); + if (wire != WireId()) + wire_info(wire).bel_pins.push_back(BelPin{bel, name}); } void Arch::addBelInout(BelId bel, IdString name, WireId wire) @@ -143,7 +145,8 @@ void Arch::addBelInout(BelId bel, IdString name, WireId wire) pi.wire = wire; pi.type = PORT_INOUT; - wire_info(wire).bel_pins.push_back(BelPin{bel, name}); + if (wire != WireId()) + wire_info(wire).bel_pins.push_back(BelPin{bel, name}); } void Arch::addGroupBel(IdStringList group, BelId bel) { groups[group].bels.push_back(bel); } -- cgit v1.2.3