From f88ddf85b296e486731a79ec2c6fc698169a0657 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Mon, 1 Apr 2019 17:44:27 +0100
Subject: generic: Add simple primitive library

Signed-off-by: David Shah <dave@ds0.me>
---
 generic/synth/cells_map.v | 12 ++++++++++
 generic/synth/prims.v     | 59 +++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 71 insertions(+)
 create mode 100644 generic/synth/cells_map.v
 create mode 100644 generic/synth/prims.v

(limited to 'generic/synth')

diff --git a/generic/synth/cells_map.v b/generic/synth/cells_map.v
new file mode 100644
index 00000000..adbccb52
--- /dev/null
+++ b/generic/synth/cells_map.v
@@ -0,0 +1,12 @@
+module \$lut (A, Y);
+	parameter WIDTH = 0;
+	parameter LUT = 0;
+	input [WIDTH-1:0] A;
+	output Y;
+
+	LUT #(.K(`LUT_K), .INIT(LUT)) _TECHMAP_REPLACE_ (.I(A), .Q(Y));
+endmodule
+
+
+module  \$_DFF_N_ (input D, C, output Q); DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
+module  \$_DFF_P_ (input D, C, output Q); DFF  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(!C)); endmodule
diff --git a/generic/synth/prims.v b/generic/synth/prims.v
new file mode 100644
index 00000000..95fcfac7
--- /dev/null
+++ b/generic/synth/prims.v
@@ -0,0 +1,59 @@
+// LUT and DFF are combined to a GENERIC_SLICE
+
+module LUT #(
+	parameter K = 4,
+	parameter [2**K-1:0] INIT = 0,
+) (
+	input [K-1:0] I,
+	output Q
+);
+	assign Q = INIT[I];
+endmodule
+
+module DFF (
+	input CLK, D,
+	output reg Q
+);
+	always @(posedge CLK)
+		Q <= D;
+endmodule
+
+module GENERIC_SLICE #(
+	parameter K = 4,
+	parameter [2**K-1:0] INIT = 0,
+	parameter FF_USED = 1'b0
+) (
+	input CLK,
+	input [K-1:0] I,
+	output Q
+);
+	
+	wire lut_q;
+	LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(lut_q));
+
+	generate if (FF_USED)
+		DFF dff_i(.CLK(CLK), .D(lut_q), .Q(Q));
+	else
+		assign Q = lut_q; 
+	endgenerate
+endmodule
+
+module GENERIC_IOB #(
+	parameter INPUT_USED = 1'b0,
+	parameter OUTPUT_USED = 1'b0,
+	parameter ENABLE_USED = 1'b0
+) (
+	inout PAD,
+	input I, EN,
+	output O
+);
+	generate if (OUTPUT_USED && ENABLE_USED)
+		assign PAD = EN ? I : 1'bz;
+	else if (OUTPUT_USED)
+		assign PAD = I;
+	endgenerate
+
+	generate if (INPUT_USED)
+		assign O = PAD;
+	endgenerate
+endmodule
\ No newline at end of file
-- 
cgit v1.2.3