From 50fd8aa01fde3426ff74fcf9b0126a24f279efca Mon Sep 17 00:00:00 2001 From: David Shah Date: Sun, 31 Mar 2019 17:54:52 +0100 Subject: generic: Place a single SLICE Signed-off-by: David Shah --- generic/examples/simple.py | 3 +++ generic/examples/simple.v | 15 +++++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 generic/examples/simple.py create mode 100644 generic/examples/simple.v (limited to 'generic/examples') diff --git a/generic/examples/simple.py b/generic/examples/simple.py new file mode 100644 index 00000000..da41dc5b --- /dev/null +++ b/generic/examples/simple.py @@ -0,0 +1,3 @@ +ctx.addBel(name="SLICE_X1Y1", type="SLICE_LUT4", loc=Loc(1, 1, 0), gb=False) +ctx.addBel(name="IO0_I", type="$nextpnr_ibuf", loc=Loc(0, 0, 0), gb=False) +ctx.addBel(name="IO1_O", type="$nextpnr_obuf", loc=Loc(1, 0, 0), gb=False) \ No newline at end of file diff --git a/generic/examples/simple.v b/generic/examples/simple.v new file mode 100644 index 00000000..6d337101 --- /dev/null +++ b/generic/examples/simple.v @@ -0,0 +1,15 @@ +(* blackbox *) +module SLICE_LUT4( + input I0, I1, I2, I3, + input CLK, + output Q +); +parameter INIT = 16'h0000; +parameter FF_USED = 1'b0; +endmodule + +module top(input a, output q); + +SLICE_LUT4 sl_i(.I0(a), .Q(q)); + +endmodule \ No newline at end of file -- cgit v1.2.3 From ca918078bfe6c4b1a279c7df7c59fb9de0f9710a Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 1 Apr 2019 19:13:16 +0100 Subject: generic: Add a simple packer for generic SLICEs and IOBs Signed-off-by: David Shah --- generic/examples/simple.py | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) (limited to 'generic/examples') diff --git a/generic/examples/simple.py b/generic/examples/simple.py index da41dc5b..17808fc7 100644 --- a/generic/examples/simple.py +++ b/generic/examples/simple.py @@ -1,3 +1,16 @@ -ctx.addBel(name="SLICE_X1Y1", type="SLICE_LUT4", loc=Loc(1, 1, 0), gb=False) -ctx.addBel(name="IO0_I", type="$nextpnr_ibuf", loc=Loc(0, 0, 0), gb=False) -ctx.addBel(name="IO1_O", type="$nextpnr_obuf", loc=Loc(1, 0, 0), gb=False) \ No newline at end of file +X = 12 +Y = 12 + +def is_io(x, y): + return x == 0 or x == X-1 or y == 0 or y == Y-1 + + +for x in range(X): + for y in range(Y): + if is_io(x, y): + if x == y: + continue + for z in range(2): + ctx.addBel(name="X%dY%d_IO%d" % (x, y, z), type="GENERIC_IOB", loc=Loc(x, y, z), gb=False) + else: + ctx.addBel(name="X%dY%d_SLICE%d" % (x, y, z), type="GENERIC_SLICE", loc=Loc(x, y, z), gb=False) -- cgit v1.2.3 From 6a383cd4c57db1f8bab6416daffdb24c0eb093c6 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 1 Apr 2019 19:48:51 +0100 Subject: generic: Simple procedural example works Signed-off-by: David Shah --- generic/examples/simple.py | 75 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 73 insertions(+), 2 deletions(-) (limited to 'generic/examples') diff --git a/generic/examples/simple.py b/generic/examples/simple.py index 17808fc7..b8ca3f78 100644 --- a/generic/examples/simple.py +++ b/generic/examples/simple.py @@ -1,16 +1,87 @@ +# Grid size including IOBs at edges X = 12 Y = 12 +# SLICEs per tile +Z = 8 +# LUT input count +K = 4 +# Number of local wires +L = Z*(K+1) + 8 +# "Sparsity" of bel input wire pips +Si = 4 +# "Sparsity" of Q to local wire pips +Sq = 4 +# "Sparsity" of local to neighbour local wire pips +Sl = 8 def is_io(x, y): return x == 0 or x == X-1 or y == 0 or y == Y-1 - for x in range(X): for y in range(Y): + # Bel port wires + for z in range(Z): + ctx.addWire(name="X%dY%dZ%d_CLK" % (x, y, z), type="BEL_CLK", x=x, y=y) + ctx.addWire(name="X%dY%dZ%d_Q" % (x, y, z), type="BEL_Q", x=x, y=y) + for i in range(K): + ctx.addWire(name="X%dY%dZ%d_I%d" % (x, y, z, i), type="BEL_I", x=x, y=y) + # Local wires + for l in range(L): + ctx.addWire(name="X%dY%d_LOCAL%d" % (x, y, l), type="LOCAL", x=x, y=y) + # Create bels if is_io(x, y): if x == y: continue for z in range(2): ctx.addBel(name="X%dY%d_IO%d" % (x, y, z), type="GENERIC_IOB", loc=Loc(x, y, z), gb=False) + ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="I", wire="X%dY%dZ%d_I0" % (x, y, z)) + ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="EN", wire="X%dY%dZ%d_I1" % (x, y, z)) + ctx.addBelOutput(bel="X%dY%d_IO%d" % (x, y, z), name="O", wire="X%dY%dZ%d_Q" % (x, y, z)) + else: - ctx.addBel(name="X%dY%d_SLICE%d" % (x, y, z), type="GENERIC_SLICE", loc=Loc(x, y, z), gb=False) + for z in range(Z): + ctx.addBel(name="X%dY%d_SLICE%d" % (x, y, z), type="GENERIC_SLICE", loc=Loc(x, y, z), gb=False) + ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="CLK", wire="X%dY%dZ%d_CLK" % (x, y, z)) + for k in range(K): + ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="I[%d]" % k, wire="X%dY%dZ%d_I%d" % (x, y, z, k)) + ctx.addBelOutput(bel="X%dY%d_SLICE%d" % (x, y, z), name="Q", wire="X%dY%dZ%d_Q" % (x, y, z)) + +for x in range(X): + for y in range(Y): + # Pips driving bel input wires + # Bel input wires are driven by every Si'th local with an offset + def create_input_pips(dst, offset, skip): + for i in range(offset % skip, L, skip): + src = "X%dY%d_LOCAL%d" % (x, y, i) + ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="BEL_INPUT", + srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0)) + for z in range(Z): + create_input_pips("X%dY%dZ%d_CLK" % (x, y, z), 0, Si) + for k in range(K): + create_input_pips("X%dY%dZ%d_I%d" % (x, y, z, k), k % Si, Si) + + # Pips from bel outputs to locals + def create_output_pips(dst, offset, skip): + for i in range(offset % skip, Z, skip): + src = "X%dY%dZ%d_Q" % (x, y, i) + ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="BEL_OUTPUT", + srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0)) + # Pips from neighbour locals to locals + def create_neighbour_pips(dst, nx, ny, offset, skip): + if nx < 0 or nx >= X or ny < 0 or ny >= Y: + return + for i in range(offset % skip, L, skip): + src = "X%dY%d_LOCAL%d" % (nx, ny, i) + ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="NEIGHBOUR", + srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0)) + for l in range(L): + dst = "X%dY%d_LOCAL%d" % (x, y, l) + create_output_pips(dst, l % Sq, Sq) + create_neighbour_pips(dst, x-1, y-1, (l + 1) % Sl, Sl) + create_neighbour_pips(dst, x-1, y, (l + 2) % Sl, Sl) + create_neighbour_pips(dst, x-1, y+1, (l + 2) % Sl, Sl) + create_neighbour_pips(dst, x, y-1, (l + 3) % Sl, Sl) + create_neighbour_pips(dst, x, y+1, (l + 4) % Sl, Sl) + create_neighbour_pips(dst, x+1, y-1, (l + 5) % Sl, Sl) + create_neighbour_pips(dst, x+1, y, (l + 6) % Sl, Sl) + create_neighbour_pips(dst, x+1, y+1, (l + 7) % Sl, Sl) \ No newline at end of file -- cgit v1.2.3 From 32327b761ab8b8c438bd91d6c32f061ffaed3454 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 1 Apr 2019 20:16:29 +0100 Subject: generic: Simple working example Signed-off-by: David Shah --- generic/examples/.gitignore | 1 + generic/examples/README.md | 11 +++++++++++ generic/examples/blinky.v | 9 +++++++++ generic/examples/report.py | 13 +++++++++++++ generic/examples/simple.sh | 4 ++++ generic/examples/simple.v | 15 --------------- 6 files changed, 38 insertions(+), 15 deletions(-) create mode 100644 generic/examples/.gitignore create mode 100644 generic/examples/README.md create mode 100644 generic/examples/blinky.v create mode 100644 generic/examples/report.py create mode 100755 generic/examples/simple.sh delete mode 100644 generic/examples/simple.v (limited to 'generic/examples') diff --git a/generic/examples/.gitignore b/generic/examples/.gitignore new file mode 100644 index 00000000..83d79a7d --- /dev/null +++ b/generic/examples/.gitignore @@ -0,0 +1 @@ +blinky.txt diff --git a/generic/examples/README.md b/generic/examples/README.md new file mode 100644 index 00000000..5eb0ea72 --- /dev/null +++ b/generic/examples/README.md @@ -0,0 +1,11 @@ +# Generic Architecture Example + +This contains a simple, artificial, example of the nextpnr generic API. + + - simple.py procedurally generates a simple FPGA architecture with IO at the edges, + logic slices in all other tiles, and interconnect only between adjacent tiles + + - report.py stores design information after place-and-route to blinky.txt in place + of real bitstream generation + + - Run blinky.sh to build an example design on the FPGA above \ No newline at end of file diff --git a/generic/examples/blinky.v b/generic/examples/blinky.v new file mode 100644 index 00000000..b7cb1b86 --- /dev/null +++ b/generic/examples/blinky.v @@ -0,0 +1,9 @@ +module top(input clk, output reg [7:0] leds); + +reg [25:0] ctr; +always @(posedge clk) + ctr <= ctr + 1'b1; + +assign leds = ctr[25:18]; + +endmodule \ No newline at end of file diff --git a/generic/examples/report.py b/generic/examples/report.py new file mode 100644 index 00000000..c43367fa --- /dev/null +++ b/generic/examples/report.py @@ -0,0 +1,13 @@ +with open("blinky.txt", "w") as f: + for nname, net in ctx.nets: + print("# Net %s" % nname, file=f) + # FIXME: Pip ordering + for wire, pip in net.wires: + if pip.pip != "": + print("%s" % pip.pip, file=f) + print("", file=f) + for cname, cell in ctx.cells: + print("# Cell %s at %s" % (cname, cell.bel), file=f) + for param, val in cell.params: + print("%s.%s %s" % (cell.bel, param, val), file=f) + print("", file=f) \ No newline at end of file diff --git a/generic/examples/simple.sh b/generic/examples/simple.sh new file mode 100755 index 00000000..ed800639 --- /dev/null +++ b/generic/examples/simple.sh @@ -0,0 +1,4 @@ +#!/usr/bin/bash +set -ex +yosys -p "tcl ../synth/synth_generic.tcl 4 blinky.json" blinky.v +../../nextpnr-generic --pre-pack simple.py --json blinky.json --post-route report.py \ No newline at end of file diff --git a/generic/examples/simple.v b/generic/examples/simple.v deleted file mode 100644 index 6d337101..00000000 --- a/generic/examples/simple.v +++ /dev/null @@ -1,15 +0,0 @@ -(* blackbox *) -module SLICE_LUT4( - input I0, I1, I2, I3, - input CLK, - output Q -); -parameter INIT = 16'h0000; -parameter FF_USED = 1'b0; -endmodule - -module top(input a, output q); - -SLICE_LUT4 sl_i(.I0(a), .Q(q)); - -endmodule \ No newline at end of file -- cgit v1.2.3 From 6fffe24177f9b99d6c332c18e343648cf33d4397 Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 3 Apr 2019 16:08:33 +0100 Subject: generic: GUI Python bindings Signed-off-by: David Shah --- generic/examples/simple.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'generic/examples') diff --git a/generic/examples/simple.py b/generic/examples/simple.py index b8ca3f78..2628c041 100644 --- a/generic/examples/simple.py +++ b/generic/examples/simple.py @@ -14,6 +14,10 @@ Sq = 4 # "Sparsity" of local to neighbour local wire pips Sl = 8 +# Create graphic elements +# Bels +ctx.addDecalGraphic("bel", GraphicElement(type=TYPE_BOX, style=STYLE_INACTIVE, x1=0, y1=0, x2=0.2, y2=(1/(Z+1))-0.02, z=0)) + def is_io(x, y): return x == 0 or x == X-1 or y == 0 or y == Y-1 @@ -37,7 +41,7 @@ for x in range(X): ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="I", wire="X%dY%dZ%d_I0" % (x, y, z)) ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="EN", wire="X%dY%dZ%d_I1" % (x, y, z)) ctx.addBelOutput(bel="X%dY%d_IO%d" % (x, y, z), name="O", wire="X%dY%dZ%d_Q" % (x, y, z)) - + ctx.setBelDecal(bel="X%dY%d_IO%d" % (x, y, z), decalxy=ctx.DecalXY("bel", 0.6, z * (1/(Z+1)))) else: for z in range(Z): ctx.addBel(name="X%dY%d_SLICE%d" % (x, y, z), type="GENERIC_SLICE", loc=Loc(x, y, z), gb=False) @@ -45,6 +49,7 @@ for x in range(X): for k in range(K): ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="I[%d]" % k, wire="X%dY%dZ%d_I%d" % (x, y, z, k)) ctx.addBelOutput(bel="X%dY%d_SLICE%d" % (x, y, z), name="Q", wire="X%dY%dZ%d_Q" % (x, y, z)) + ctx.setBelDecal(bel="X%dY%d_SLICE%d" % (x, y, z), decalxy=ctx.DecalXY("bel", 0.6, z * (1/(Z+1)))) for x in range(X): for y in range(Y): -- cgit v1.2.3 From 3f98084021b64420c36c171cc1245248d6968f03 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 4 Apr 2019 15:40:48 +0100 Subject: generic: Improve example Signed-off-by: David Shah --- generic/examples/README.md | 2 +- generic/examples/simple.py | 32 ++++++++++++++++---------------- 2 files changed, 17 insertions(+), 17 deletions(-) (limited to 'generic/examples') diff --git a/generic/examples/README.md b/generic/examples/README.md index 5eb0ea72..4641f542 100644 --- a/generic/examples/README.md +++ b/generic/examples/README.md @@ -8,4 +8,4 @@ This contains a simple, artificial, example of the nextpnr generic API. - report.py stores design information after place-and-route to blinky.txt in place of real bitstream generation - - Run blinky.sh to build an example design on the FPGA above \ No newline at end of file + - Run simple.sh to build an example design on the FPGA above \ No newline at end of file diff --git a/generic/examples/simple.py b/generic/examples/simple.py index 2628c041..f87a6049 100644 --- a/generic/examples/simple.py +++ b/generic/examples/simple.py @@ -2,21 +2,21 @@ X = 12 Y = 12 # SLICEs per tile -Z = 8 +N = 8 # LUT input count K = 4 # Number of local wires -L = Z*(K+1) + 8 -# "Sparsity" of bel input wire pips +Wl = N*(K+1) + 8 +# 1/Fc for bel input wire pips Si = 4 -# "Sparsity" of Q to local wire pips +# 1/Fc for Q to local wire pips Sq = 4 -# "Sparsity" of local to neighbour local wire pips +# ~1/Fc local to neighbour local wire pips Sl = 8 # Create graphic elements # Bels -ctx.addDecalGraphic("bel", GraphicElement(type=TYPE_BOX, style=STYLE_INACTIVE, x1=0, y1=0, x2=0.2, y2=(1/(Z+1))-0.02, z=0)) +ctx.addDecalGraphic("bel", GraphicElement(type=TYPE_BOX, style=STYLE_INACTIVE, x1=0, y1=0, x2=0.2, y2=(1/(N+1))-0.02, z=0)) def is_io(x, y): return x == 0 or x == X-1 or y == 0 or y == Y-1 @@ -24,13 +24,13 @@ def is_io(x, y): for x in range(X): for y in range(Y): # Bel port wires - for z in range(Z): + for z in range(N): ctx.addWire(name="X%dY%dZ%d_CLK" % (x, y, z), type="BEL_CLK", x=x, y=y) ctx.addWire(name="X%dY%dZ%d_Q" % (x, y, z), type="BEL_Q", x=x, y=y) for i in range(K): ctx.addWire(name="X%dY%dZ%d_I%d" % (x, y, z, i), type="BEL_I", x=x, y=y) # Local wires - for l in range(L): + for l in range(Wl): ctx.addWire(name="X%dY%d_LOCAL%d" % (x, y, l), type="LOCAL", x=x, y=y) # Create bels if is_io(x, y): @@ -41,33 +41,33 @@ for x in range(X): ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="I", wire="X%dY%dZ%d_I0" % (x, y, z)) ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="EN", wire="X%dY%dZ%d_I1" % (x, y, z)) ctx.addBelOutput(bel="X%dY%d_IO%d" % (x, y, z), name="O", wire="X%dY%dZ%d_Q" % (x, y, z)) - ctx.setBelDecal(bel="X%dY%d_IO%d" % (x, y, z), decalxy=ctx.DecalXY("bel", 0.6, z * (1/(Z+1)))) + ctx.setBelDecal(bel="X%dY%d_IO%d" % (x, y, z), decalxy=ctx.DecalXY("bel", 0.6, z * (1/(N+1)))) else: - for z in range(Z): + for z in range(N): ctx.addBel(name="X%dY%d_SLICE%d" % (x, y, z), type="GENERIC_SLICE", loc=Loc(x, y, z), gb=False) ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="CLK", wire="X%dY%dZ%d_CLK" % (x, y, z)) for k in range(K): ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="I[%d]" % k, wire="X%dY%dZ%d_I%d" % (x, y, z, k)) ctx.addBelOutput(bel="X%dY%d_SLICE%d" % (x, y, z), name="Q", wire="X%dY%dZ%d_Q" % (x, y, z)) - ctx.setBelDecal(bel="X%dY%d_SLICE%d" % (x, y, z), decalxy=ctx.DecalXY("bel", 0.6, z * (1/(Z+1)))) + ctx.setBelDecal(bel="X%dY%d_SLICE%d" % (x, y, z), decalxy=ctx.DecalXY("bel", 0.6, z * (1/(N+1)))) for x in range(X): for y in range(Y): # Pips driving bel input wires # Bel input wires are driven by every Si'th local with an offset def create_input_pips(dst, offset, skip): - for i in range(offset % skip, L, skip): + for i in range(offset % skip, Wl, skip): src = "X%dY%d_LOCAL%d" % (x, y, i) ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="BEL_INPUT", srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0)) - for z in range(Z): + for z in range(N): create_input_pips("X%dY%dZ%d_CLK" % (x, y, z), 0, Si) for k in range(K): create_input_pips("X%dY%dZ%d_I%d" % (x, y, z, k), k % Si, Si) # Pips from bel outputs to locals def create_output_pips(dst, offset, skip): - for i in range(offset % skip, Z, skip): + for i in range(offset % skip, N, skip): src = "X%dY%dZ%d_Q" % (x, y, i) ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="BEL_OUTPUT", srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0)) @@ -75,11 +75,11 @@ for x in range(X): def create_neighbour_pips(dst, nx, ny, offset, skip): if nx < 0 or nx >= X or ny < 0 or ny >= Y: return - for i in range(offset % skip, L, skip): + for i in range(offset % skip, Wl, skip): src = "X%dY%d_LOCAL%d" % (nx, ny, i) ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="NEIGHBOUR", srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0)) - for l in range(L): + for l in range(Wl): dst = "X%dY%d_LOCAL%d" % (x, y, l) create_output_pips(dst, l % Sq, Sq) create_neighbour_pips(dst, x-1, y-1, (l + 1) % Sl, Sl) -- cgit v1.2.3 From f0cd51e6bc58f3dfd1185fd53ad970ba634359f2 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 4 Apr 2019 16:30:47 +0100 Subject: generic: Cell timing support Signed-off-by: David Shah --- generic/examples/README.md | 2 ++ generic/examples/simple.sh | 2 +- generic/examples/simple_timing.py | 15 +++++++++++++++ 3 files changed, 18 insertions(+), 1 deletion(-) create mode 100644 generic/examples/simple_timing.py (limited to 'generic/examples') diff --git a/generic/examples/README.md b/generic/examples/README.md index 4641f542..dd154a51 100644 --- a/generic/examples/README.md +++ b/generic/examples/README.md @@ -4,6 +4,8 @@ This contains a simple, artificial, example of the nextpnr generic API. - simple.py procedurally generates a simple FPGA architecture with IO at the edges, logic slices in all other tiles, and interconnect only between adjacent tiles + + - simple_timing.py annotates cells with timing data (this is a separate script that must be run after packing) - report.py stores design information after place-and-route to blinky.txt in place of real bitstream generation diff --git a/generic/examples/simple.sh b/generic/examples/simple.sh index ed800639..2e8d6180 100755 --- a/generic/examples/simple.sh +++ b/generic/examples/simple.sh @@ -1,4 +1,4 @@ #!/usr/bin/bash set -ex yosys -p "tcl ../synth/synth_generic.tcl 4 blinky.json" blinky.v -../../nextpnr-generic --pre-pack simple.py --json blinky.json --post-route report.py \ No newline at end of file +../../nextpnr-generic --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route report.py \ No newline at end of file diff --git a/generic/examples/simple_timing.py b/generic/examples/simple_timing.py new file mode 100644 index 00000000..a955c8d7 --- /dev/null +++ b/generic/examples/simple_timing.py @@ -0,0 +1,15 @@ +for cname, cell in ctx.cells: + if cell.type != "GENERIC_SLICE": + continue + if cname in ("$PACKER_GND", "$PACKER_VCC"): + continue + K = int(cell.params["K"]) + if cell.params["FF_USED"] == "1": + ctx.addCellTimingClock(cell=cname, port="CLK") + for i in range(K): + ctx.addCellTimingSetupHold(cell=cname, port="I[%d]" % i, clock="CLK", + setup=ctx.getDelayFromNS(0.2), hold=ctx.getDelayFromNS(0)) + ctx.addCellTimingClockToOut(cell=cname, port="Q", clock="CLK", clktoq=ctx.getDelayFromNS(0.2)) + else: + for i in range(K): + ctx.addCellTimingDelay(cell=cname, fromPort="I[%d]" % i, toPort="Q", delay=ctx.getDelayFromNS(0.2)) \ No newline at end of file -- cgit v1.2.3 From 48c4c1ed0561e643a591ed7fca21c69954abd8d2 Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 17 Apr 2019 11:00:23 +0100 Subject: generic/examples: Add FASM writer Python script Signed-off-by: David Shah --- generic/examples/.gitignore | 4 ++- generic/examples/README.md | 5 ++-- generic/examples/__init__.py | 0 generic/examples/bitstream.py | 17 +++++++++++++ generic/examples/report.py | 13 ---------- generic/examples/simple.py | 22 +---------------- generic/examples/simple.sh | 2 +- generic/examples/simple_config.py | 15 +++++++++++ generic/examples/write_fasm.py | 52 +++++++++++++++++++++++++++++++++++++++ 9 files changed, 92 insertions(+), 38 deletions(-) create mode 100644 generic/examples/__init__.py create mode 100644 generic/examples/bitstream.py delete mode 100644 generic/examples/report.py create mode 100644 generic/examples/simple_config.py create mode 100644 generic/examples/write_fasm.py (limited to 'generic/examples') diff --git a/generic/examples/.gitignore b/generic/examples/.gitignore index 83d79a7d..38e95de5 100644 --- a/generic/examples/.gitignore +++ b/generic/examples/.gitignore @@ -1 +1,3 @@ -blinky.txt +blinky.fasm +__pycache__ +*.pyc diff --git a/generic/examples/README.md b/generic/examples/README.md index dd154a51..9fd106d9 100644 --- a/generic/examples/README.md +++ b/generic/examples/README.md @@ -7,7 +7,8 @@ This contains a simple, artificial, example of the nextpnr generic API. - simple_timing.py annotates cells with timing data (this is a separate script that must be run after packing) - - report.py stores design information after place-and-route to blinky.txt in place - of real bitstream generation + - write_fasm.py uses the nextpnr Python API to write a FASM file for a design + + - bitstream.py uses write_fasm.py to create a FASM ("FPGA assembly") file for the place-and-routed design - Run simple.sh to build an example design on the FPGA above \ No newline at end of file diff --git a/generic/examples/__init__.py b/generic/examples/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/generic/examples/bitstream.py b/generic/examples/bitstream.py new file mode 100644 index 00000000..1ab94f0c --- /dev/null +++ b/generic/examples/bitstream.py @@ -0,0 +1,17 @@ +from write_fasm import * +from simple_config import K + +# Need to tell FASM generator how to write parameters +# (celltype, parameter) -> ParameterConfig +param_map = { + ("GENERIC_SLICE", "K"): ParameterConfig(write=False), + ("GENERIC_SLICE", "INIT"): ParameterConfig(write=True, numeric=True, width=2**K), + ("GENERIC_SLICE", "FF_USED"): ParameterConfig(write=True, numeric=True, width=1), + + ("GENERIC_IOB", "INPUT_USED"): ParameterConfig(write=True, numeric=True, width=1), + ("GENERIC_IOB", "OUTPUT_USED"): ParameterConfig(write=True, numeric=True, width=1), + ("GENERIC_IOB", "ENABLE_USED"): ParameterConfig(write=True, numeric=True, width=1), +} + +with open("blinky.fasm", "w") as f: + write_fasm(ctx, param_map, f) \ No newline at end of file diff --git a/generic/examples/report.py b/generic/examples/report.py deleted file mode 100644 index c43367fa..00000000 --- a/generic/examples/report.py +++ /dev/null @@ -1,13 +0,0 @@ -with open("blinky.txt", "w") as f: - for nname, net in ctx.nets: - print("# Net %s" % nname, file=f) - # FIXME: Pip ordering - for wire, pip in net.wires: - if pip.pip != "": - print("%s" % pip.pip, file=f) - print("", file=f) - for cname, cell in ctx.cells: - print("# Cell %s at %s" % (cname, cell.bel), file=f) - for param, val in cell.params: - print("%s.%s %s" % (cell.bel, param, val), file=f) - print("", file=f) \ No newline at end of file diff --git a/generic/examples/simple.py b/generic/examples/simple.py index f87a6049..9339b68a 100644 --- a/generic/examples/simple.py +++ b/generic/examples/simple.py @@ -1,22 +1,4 @@ -# Grid size including IOBs at edges -X = 12 -Y = 12 -# SLICEs per tile -N = 8 -# LUT input count -K = 4 -# Number of local wires -Wl = N*(K+1) + 8 -# 1/Fc for bel input wire pips -Si = 4 -# 1/Fc for Q to local wire pips -Sq = 4 -# ~1/Fc local to neighbour local wire pips -Sl = 8 - -# Create graphic elements -# Bels -ctx.addDecalGraphic("bel", GraphicElement(type=TYPE_BOX, style=STYLE_INACTIVE, x1=0, y1=0, x2=0.2, y2=(1/(N+1))-0.02, z=0)) +from simple_config import * def is_io(x, y): return x == 0 or x == X-1 or y == 0 or y == Y-1 @@ -41,7 +23,6 @@ for x in range(X): ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="I", wire="X%dY%dZ%d_I0" % (x, y, z)) ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="EN", wire="X%dY%dZ%d_I1" % (x, y, z)) ctx.addBelOutput(bel="X%dY%d_IO%d" % (x, y, z), name="O", wire="X%dY%dZ%d_Q" % (x, y, z)) - ctx.setBelDecal(bel="X%dY%d_IO%d" % (x, y, z), decalxy=ctx.DecalXY("bel", 0.6, z * (1/(N+1)))) else: for z in range(N): ctx.addBel(name="X%dY%d_SLICE%d" % (x, y, z), type="GENERIC_SLICE", loc=Loc(x, y, z), gb=False) @@ -49,7 +30,6 @@ for x in range(X): for k in range(K): ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="I[%d]" % k, wire="X%dY%dZ%d_I%d" % (x, y, z, k)) ctx.addBelOutput(bel="X%dY%d_SLICE%d" % (x, y, z), name="Q", wire="X%dY%dZ%d_Q" % (x, y, z)) - ctx.setBelDecal(bel="X%dY%d_SLICE%d" % (x, y, z), decalxy=ctx.DecalXY("bel", 0.6, z * (1/(N+1)))) for x in range(X): for y in range(Y): diff --git a/generic/examples/simple.sh b/generic/examples/simple.sh index 2e8d6180..576a6418 100755 --- a/generic/examples/simple.sh +++ b/generic/examples/simple.sh @@ -1,4 +1,4 @@ #!/usr/bin/bash set -ex yosys -p "tcl ../synth/synth_generic.tcl 4 blinky.json" blinky.v -../../nextpnr-generic --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route report.py \ No newline at end of file +../../nextpnr-generic --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route bitstream.py \ No newline at end of file diff --git a/generic/examples/simple_config.py b/generic/examples/simple_config.py new file mode 100644 index 00000000..dfb38f1c --- /dev/null +++ b/generic/examples/simple_config.py @@ -0,0 +1,15 @@ +# Grid size including IOBs at edges +X = 12 +Y = 12 +# SLICEs per tile +N = 8 +# LUT input count +K = 4 +# Number of local wires +Wl = N*(K+1) + 8 +# 1/Fc for bel input wire pips +Si = 4 +# 1/Fc for Q to local wire pips +Sq = 4 +# ~1/Fc local to neighbour local wire pips +Sl = 8 \ No newline at end of file diff --git a/generic/examples/write_fasm.py b/generic/examples/write_fasm.py new file mode 100644 index 00000000..fb55c41d --- /dev/null +++ b/generic/examples/write_fasm.py @@ -0,0 +1,52 @@ +from collections import namedtuple + +""" + write: set to True to enable writing this parameter to FASM + + numeric: set to True to write this parameter as a bit array (width>1) or + single bit (width==1) named after the parameter. Otherwise this + parameter will be written as `name.value` + + width: width of numeric parameter (ignored for non-numeric parameters) + + alias: an alternative name for this parameter (parameter name used if alias + is None) +""" +ParameterConfig = namedtuple('ParameterConfig', 'write numeric width alias') + +# FIXME use defaults= once Python 3.7 is standard +ParameterConfig.__new__.__defaults__ = (False, True, 1, None) + + +""" +Write a design as FASM + + ctx: nextpnr context + paramCfg: ParameterConfig describing how to write parameters + f: output file +""" +def write_fasm(ctx, paramCfg, f): + for nname, net in sorted(ctx.nets, key=lambda x: str(x[1].name)): + print("# Net %s" % nname, file=f) + for wire, pip in sorted(net.wires, key=lambda x: str(x[1])): + if pip.pip != "": + print("%s" % pip.pip, file=f) + print("", file=f) + for cname, cell in sorted(ctx.cells, key=lambda x: str(x[1].name)): + print("# Cell %s at %s" % (cname, cell.bel), file=f) + for param, val in sorted(cell.params, key=lambda x: str(x)): + cfg = paramCfg[(cell.type, param)] + if not cfg.write: + continue + fasm_name = cfg.alias if cfg.alias is not None else param + if cfg.numeric: + if cfg.width == 1: + if int(val) != 0: + print("%s.%s" % (cell.bel, fasm_name), file=f) + else: + # Parameters with width >32 are direct binary, otherwise denary + binval = val if cfg.width > 32 else "{:0{}b}".format(int(val), cfg.width) + print("%s.%s[%d:0] = %d'b%s" % (cell.bel, fasm_name, cfg.width-1, cfg.width, binval), file=f) + else: + print("%s.%s.%s" % (cell.bel, fasm_name, val), file=f) + print("", file=f) \ No newline at end of file -- cgit v1.2.3 From 9fa13b5adcb4bfb193645fee0091c5c51c88c17b Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 17 Apr 2019 11:12:58 +0100 Subject: pybindings: make errors in Python scripts stop nextpnr execution Signed-off-by: David Shah --- generic/examples/write_fasm.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'generic/examples') diff --git a/generic/examples/write_fasm.py b/generic/examples/write_fasm.py index fb55c41d..1f279b63 100644 --- a/generic/examples/write_fasm.py +++ b/generic/examples/write_fasm.py @@ -22,7 +22,7 @@ ParameterConfig.__new__.__defaults__ = (False, True, 1, None) Write a design as FASM ctx: nextpnr context - paramCfg: ParameterConfig describing how to write parameters + paramCfg: map from (celltype, parametername) -> ParameterConfig describing how to write parameters f: output file """ def write_fasm(ctx, paramCfg, f): -- cgit v1.2.3 From c33da42365d36f740ed2b618235efcd4c93701f0 Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 17 Apr 2019 11:15:35 +0100 Subject: ci: Run generic example simple.sh Signed-off-by: David Shah --- generic/examples/simple.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'generic/examples') diff --git a/generic/examples/simple.sh b/generic/examples/simple.sh index 576a6418..8ae903f9 100755 --- a/generic/examples/simple.sh +++ b/generic/examples/simple.sh @@ -1,4 +1,4 @@ -#!/usr/bin/bash +#!/usr/bin/env bash set -ex yosys -p "tcl ../synth/synth_generic.tcl 4 blinky.json" blinky.v -../../nextpnr-generic --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route bitstream.py \ No newline at end of file +${NEXTPNR:-../../nextpnr-generic} --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route bitstream.py -- cgit v1.2.3