From 761d9d9229f9c1aa5420a12c5d3e4c2aab53bb11 Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Wed, 17 Feb 2021 18:08:52 -0800
Subject: Correct some bugs in the create_bba Makefile.

Also add debug_test target to debug archcheck.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 fpga_interchange/examples/create_bba/Makefile | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

(limited to 'fpga_interchange/examples')

diff --git a/fpga_interchange/examples/create_bba/Makefile b/fpga_interchange/examples/create_bba/Makefile
index 3033daca..ffbc3103 100644
--- a/fpga_interchange/examples/create_bba/Makefile
+++ b/fpga_interchange/examples/create_bba/Makefile
@@ -30,7 +30,7 @@ include ../common.mk
 
 .DELETE_ON_ERROR:
 
-.PHONY: all chipdb
+.PHONY: all chipdb test debug_test
 
 all: chipdb
 
@@ -66,7 +66,7 @@ $(NEXTPNR_PATH)/build/bba/bbasm: | $(NEXTPNR_PATH)/build
 	cd $(NEXTPNR_PATH)/build && cmake -DARCH=fpga_interchange ..
 	make -j -C $(NEXTPNR_PATH)/build
 
-$(NEXTPNR_PATH)/fpga_interchange/chipdb.bba: build/.setup
+build/nextpnr/fpga_interchange/chipdb.bba: build/.setup
 	mkdir -p build/nextpnr/fpga_interchange
 	source build/env/bin/activate && \
 		cd build/python-fpga-interchange/ && \
@@ -76,7 +76,7 @@ $(NEXTPNR_PATH)/fpga_interchange/chipdb.bba: build/.setup
 		RAPIDWRIGHT_PATH=$(RAPIDWRIGHT_PATH) \
 		INTERCHANGE_PATH=$(INTERCHANGE_PATH)
 
-$(BBA_PATH): $(NEXTPNR_PATH)/build/bba/bbasm $(NEXTPNR_PATH)/fpga_interchange/chipdb.bba
+$(BBA_PATH): $(NEXTPNR_PATH)/build/bba/bbasm build/nextpnr/fpga_interchange/chipdb.bba
 	$(NEXTPNR_PATH)/build/bba/bbasm -l build/nextpnr/fpga_interchange/chipdb.bba $(BBA_PATH)
 
 chipdb: $(BBA_PATH)
@@ -87,5 +87,11 @@ test: chipdb
 		--package csg324 \
 		--test
 
+debug_test: chipdb
+	gdb --args $(NEXTPNR_PATH)/build/nextpnr-fpga_interchange \
+		--chipdb $(BBA_PATH) \
+		--package csg324 \
+		--test
+
 clean:
 	rm -rf build
-- 
cgit v1.2.3


From 3e5a23ed5b25570c33669dfd8bdd226016968bb5 Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Wed, 17 Feb 2021 18:34:32 -0800
Subject: Add tests to confirm constant routing import.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 fpga_interchange/examples/archcheck/Makefile       |  7 ++++++
 fpga_interchange/examples/archcheck/test_data.yaml | 29 ++++++++++++++++++++++
 2 files changed, 36 insertions(+)

(limited to 'fpga_interchange/examples')

diff --git a/fpga_interchange/examples/archcheck/Makefile b/fpga_interchange/examples/archcheck/Makefile
index cf82013b..02e1c08e 100644
--- a/fpga_interchange/examples/archcheck/Makefile
+++ b/fpga_interchange/examples/archcheck/Makefile
@@ -13,4 +13,11 @@ check: check_test_data
 check_test_data:
 	$(NEXTPNR_BIN) \
 		--chipdb $(BBA_PATH) \
+		--package $(PACKAGE) \
+		--run $(NEXTPNR_PATH)/python/check_arch_api.py
+
+debug_check_test_data:
+	gdb --args $(NEXTPNR_BIN) \
+		--chipdb $(BBA_PATH) \
+		--package $(PACKAGE) \
 		--run $(NEXTPNR_PATH)/python/check_arch_api.py
diff --git a/fpga_interchange/examples/archcheck/test_data.yaml b/fpga_interchange/examples/archcheck/test_data.yaml
index b41112cf..268d180a 100644
--- a/fpga_interchange/examples/archcheck/test_data.yaml
+++ b/fpga_interchange/examples/archcheck/test_data.yaml
@@ -1,7 +1,36 @@
 pip_test:
     - src_wire: CLBLM_R_X11Y93/CLBLM_L_D3
       dst_wire: SLICE_X15Y93.SLICEL/D3
+pip_chain_test:
+    - wires:
+        - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+        - $CONSTANTS_X0Y0/$GND_NODE
+        - TIEOFF_X3Y145.TIEOFF/$GND_SITE_WIRE
+        - TIEOFF_X3Y145.TIEOFF/HARD0GND_HARD0
+        - INT_R_X3Y145/GND_WIRE
+    - wires:
+        - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
+        - $CONSTANTS_X0Y0/$VCC_NODE
+        - TIEOFF_X3Y145.TIEOFF/$VCC_SITE_WIRE
+        - TIEOFF_X3Y145.TIEOFF/HARD1VCC_HARD1
+        - INT_R_X3Y145/VCC_WIRE
+    - wires:
+        - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
+        - $CONSTANTS_X0Y0/$VCC_NODE
+        - SLICE_X3Y145.SLICEL/$VCC_SITE_WIRE
+        - SLICE_X3Y145.SLICEL/CEUSEDVCC_HARD1
+    - wires:
+        - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+        - $CONSTANTS_X0Y0/$GND_NODE
+        - SLICE_X3Y145.SLICEL/$GND_SITE_WIRE
+        - SLICE_X3Y145.SLICEL/SRUSEDGND_HARD0
 bel_pin_test:
     - bel: SLICE_X15Y93.SLICEL/D6LUT
       pin: A3
       wire: SLICE_X15Y93.SLICEL/D3
+    - bel: $CONSTANTS_X0Y0.$CONSTANTS/GND
+      pin: G
+      wire: $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+    - bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC
+      pin: P
+      wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
-- 
cgit v1.2.3


From cf554f9338db84fa0d12afd83e10f7791e62efa1 Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Thu, 18 Feb 2021 16:51:05 -0800
Subject: Add constant network test case.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 fpga_interchange/examples/const_wire/Makefile |  8 ++++++++
 fpga_interchange/examples/const_wire/run.tcl  | 14 ++++++++++++++
 fpga_interchange/examples/const_wire/wire.v   |  6 ++++++
 fpga_interchange/examples/const_wire/wire.xdc |  5 +++++
 fpga_interchange/examples/template.mk         |  9 +++++++++
 5 files changed, 42 insertions(+)
 create mode 100644 fpga_interchange/examples/const_wire/Makefile
 create mode 100644 fpga_interchange/examples/const_wire/run.tcl
 create mode 100644 fpga_interchange/examples/const_wire/wire.v
 create mode 100644 fpga_interchange/examples/const_wire/wire.xdc

(limited to 'fpga_interchange/examples')

diff --git a/fpga_interchange/examples/const_wire/Makefile b/fpga_interchange/examples/const_wire/Makefile
new file mode 100644
index 00000000..49194f53
--- /dev/null
+++ b/fpga_interchange/examples/const_wire/Makefile
@@ -0,0 +1,8 @@
+DESIGN := wire
+DESIGN_TOP := top
+PACKAGE := csg324
+
+include ../template.mk
+
+build/wire.json: wire.v | build
+	yosys -c run.tcl
diff --git a/fpga_interchange/examples/const_wire/run.tcl b/fpga_interchange/examples/const_wire/run.tcl
new file mode 100644
index 00000000..9127be20
--- /dev/null
+++ b/fpga_interchange/examples/const_wire/run.tcl
@@ -0,0 +1,14 @@
+yosys -import
+
+read_verilog wire.v
+
+synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json build/wire.json
diff --git a/fpga_interchange/examples/const_wire/wire.v b/fpga_interchange/examples/const_wire/wire.v
new file mode 100644
index 00000000..7905c92e
--- /dev/null
+++ b/fpga_interchange/examples/const_wire/wire.v
@@ -0,0 +1,6 @@
+module top(output o, output o2);
+
+assign o = 1'b0;
+assign o2 = 1'b1;
+
+endmodule
diff --git a/fpga_interchange/examples/const_wire/wire.xdc b/fpga_interchange/examples/const_wire/wire.xdc
new file mode 100644
index 00000000..beab748e
--- /dev/null
+++ b/fpga_interchange/examples/const_wire/wire.xdc
@@ -0,0 +1,5 @@
+set_property PACKAGE_PIN N15 [get_ports o]
+set_property PACKAGE_PIN N16 [get_ports o2]
+
+set_property IOSTANDARD LVCMOS33 [get_ports o]
+set_property IOSTANDARD LVCMOS33 [get_ports o2]
diff --git a/fpga_interchange/examples/template.mk b/fpga_interchange/examples/template.mk
index 819cdb1f..d12a4e11 100644
--- a/fpga_interchange/examples/template.mk
+++ b/fpga_interchange/examples/template.mk
@@ -46,6 +46,15 @@ build/$(DESIGN)_phys.yaml: build/$(DESIGN).phys
 
 phys_yaml: build/$(DESIGN)_phys.yaml
 
+verbose: build/$(DESIGN).netlist
+	$(NEXTPNR_BIN) \
+		--chipdb $(BBA_PATH) \
+		--xdc $(DESIGN).xdc \
+		--netlist build/$(DESIGN).netlist \
+		--phys build/$(DESIGN).phys \
+		--package $(PACKAGE) \
+		--verbose
+
 debug: build/$(DESIGN).netlist
 	gdb --args $(NEXTPNR_BIN) \
 		--chipdb $(BBA_PATH) \
-- 
cgit v1.2.3


From 15459cae91276f956d2a4734f42162d6afaf1128 Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Thu, 18 Feb 2021 16:51:36 -0800
Subject: Initial working constant network support!

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 fpga_interchange/examples/const_wire/wire.v   | 4 +++-
 fpga_interchange/examples/const_wire/wire.xdc | 4 ++++
 2 files changed, 7 insertions(+), 1 deletion(-)

(limited to 'fpga_interchange/examples')

diff --git a/fpga_interchange/examples/const_wire/wire.v b/fpga_interchange/examples/const_wire/wire.v
index 7905c92e..5b1ab692 100644
--- a/fpga_interchange/examples/const_wire/wire.v
+++ b/fpga_interchange/examples/const_wire/wire.v
@@ -1,6 +1,8 @@
-module top(output o, output o2);
+module top(output o, output o2, output o3, output o4);
 
 assign o = 1'b0;
 assign o2 = 1'b1;
+assign o3 = 1'b0;
+assign o4 = 1'b1;
 
 endmodule
diff --git a/fpga_interchange/examples/const_wire/wire.xdc b/fpga_interchange/examples/const_wire/wire.xdc
index beab748e..0d96fc45 100644
--- a/fpga_interchange/examples/const_wire/wire.xdc
+++ b/fpga_interchange/examples/const_wire/wire.xdc
@@ -1,5 +1,9 @@
 set_property PACKAGE_PIN N15 [get_ports o]
 set_property PACKAGE_PIN N16 [get_ports o2]
+set_property PACKAGE_PIN P17 [get_ports o3]
+set_property PACKAGE_PIN R17 [get_ports o4]
 
 set_property IOSTANDARD LVCMOS33 [get_ports o]
 set_property IOSTANDARD LVCMOS33 [get_ports o2]
+set_property IOSTANDARD LVCMOS33 [get_ports o3]
+set_property IOSTANDARD LVCMOS33 [get_ports o4]
-- 
cgit v1.2.3


From cd8297f54d71a5c9f47efab45b3cc93aea86d4e5 Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Fri, 19 Feb 2021 09:46:27 -0800
Subject: Move RapidWright git URI back to upstream.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 fpga_interchange/examples/create_bba/Makefile | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

(limited to 'fpga_interchange/examples')

diff --git a/fpga_interchange/examples/create_bba/Makefile b/fpga_interchange/examples/create_bba/Makefile
index ffbc3103..c29bfa82 100644
--- a/fpga_interchange/examples/create_bba/Makefile
+++ b/fpga_interchange/examples/create_bba/Makefile
@@ -38,11 +38,7 @@ build:
 	mkdir build
 
 build/RapidWright: | build
-	# FIXME: Update URL / branch as fixes are merged upstream and / or
-	# interchange branch on Xilinx/RapidWright is merged to master branch.
-	#
-	#cd build && git clone -b interchange https://github.com/Xilinx/RapidWright.git
-	cd build && git clone -b move_strlist https://github.com/litghost/RapidWright.git
+	cd build && git clone https://github.com/Xilinx/RapidWright.git
 
 build/env: | build
 	python3 -mvenv build/env
-- 
cgit v1.2.3


From 2fc353d5592b0bf9ed8428545bbd6a64312cc16e Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Fri, 19 Feb 2021 16:18:59 -0800
Subject: Add initial logic for handling dedicated interconnect situations.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 fpga_interchange/examples/ff/Makefile |  8 ++++++++
 fpga_interchange/examples/ff/ff.v     | 11 +++++++++++
 fpga_interchange/examples/ff/ff.xdc   |  9 +++++++++
 fpga_interchange/examples/ff/run.tcl  | 14 ++++++++++++++
 4 files changed, 42 insertions(+)
 create mode 100644 fpga_interchange/examples/ff/Makefile
 create mode 100644 fpga_interchange/examples/ff/ff.v
 create mode 100644 fpga_interchange/examples/ff/ff.xdc
 create mode 100644 fpga_interchange/examples/ff/run.tcl

(limited to 'fpga_interchange/examples')

diff --git a/fpga_interchange/examples/ff/Makefile b/fpga_interchange/examples/ff/Makefile
new file mode 100644
index 00000000..c6118ff7
--- /dev/null
+++ b/fpga_interchange/examples/ff/Makefile
@@ -0,0 +1,8 @@
+DESIGN := ff
+DESIGN_TOP := top
+PACKAGE := csg324
+
+include ../template.mk
+
+build/ff.json: ff.v | build
+	yosys -c run.tcl
diff --git a/fpga_interchange/examples/ff/ff.v b/fpga_interchange/examples/ff/ff.v
new file mode 100644
index 00000000..1c271042
--- /dev/null
+++ b/fpga_interchange/examples/ff/ff.v
@@ -0,0 +1,11 @@
+module top(input clk, input d, input r, output reg q);
+
+always @(posedge clk)
+begin
+    if(r)
+        q <= 1'b0;
+    else
+        q <= d;
+end
+
+endmodule
diff --git a/fpga_interchange/examples/ff/ff.xdc b/fpga_interchange/examples/ff/ff.xdc
new file mode 100644
index 00000000..3c132f1d
--- /dev/null
+++ b/fpga_interchange/examples/ff/ff.xdc
@@ -0,0 +1,9 @@
+set_property PACKAGE_PIN P17 [get_ports clk]
+set_property PACKAGE_PIN N15 [get_ports d]
+set_property PACKAGE_PIN N16 [get_ports r]
+set_property PACKAGE_PIN M17 [get_ports q]
+
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports d]
+set_property IOSTANDARD LVCMOS33 [get_ports r]
+set_property IOSTANDARD LVCMOS33 [get_ports q]
diff --git a/fpga_interchange/examples/ff/run.tcl b/fpga_interchange/examples/ff/run.tcl
new file mode 100644
index 00000000..726d86eb
--- /dev/null
+++ b/fpga_interchange/examples/ff/run.tcl
@@ -0,0 +1,14 @@
+yosys -import
+
+read_verilog ff.v
+
+synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json build/ff.json
-- 
cgit v1.2.3


From 5574455d2a20d3bb950e5dd907ef193d049a2a26 Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Fri, 19 Feb 2021 17:28:25 -0800
Subject: Working FF example now that constant merging is done.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 fpga_interchange/examples/template.mk   | 18 ++++++++++++++++++
 fpga_interchange/examples/wire/wire.xdc |  3 +++
 2 files changed, 21 insertions(+)

(limited to 'fpga_interchange/examples')

diff --git a/fpga_interchange/examples/template.mk b/fpga_interchange/examples/template.mk
index d12a4e11..c795544e 100644
--- a/fpga_interchange/examples/template.mk
+++ b/fpga_interchange/examples/template.mk
@@ -55,6 +55,15 @@ verbose: build/$(DESIGN).netlist
 		--package $(PACKAGE) \
 		--verbose
 
+verbose2: build/$(DESIGN).netlist
+	$(NEXTPNR_BIN) \
+		--chipdb $(BBA_PATH) \
+		--xdc $(DESIGN).xdc \
+		--netlist build/$(DESIGN).netlist \
+		--phys build/$(DESIGN).phys \
+		--package $(PACKAGE) \
+		--debug
+
 debug: build/$(DESIGN).netlist
 	gdb --args $(NEXTPNR_BIN) \
 		--chipdb $(BBA_PATH) \
@@ -63,6 +72,15 @@ debug: build/$(DESIGN).netlist
 		--phys build/$(DESIGN).phys \
 		--package $(PACKAGE)
 
+debug_verbose: build/$(DESIGN).netlist
+	gdb --args $(NEXTPNR_BIN) \
+		--chipdb $(BBA_PATH) \
+		--xdc $(DESIGN).xdc \
+		--netlist build/$(DESIGN).netlist \
+		--phys build/$(DESIGN).phys \
+		--package $(PACKAGE) \
+		--verbose
+
 build/$(DESIGN).dcp: build/$(DESIGN).netlist build/$(DESIGN).phys $(DESIGN).xdc
 	RAPIDWRIGHT_PATH=$(RAPIDWRIGHT_PATH) \
 		$(RAPIDWRIGHT_PATH)/scripts/invoke_rapidwright.sh \
diff --git a/fpga_interchange/examples/wire/wire.xdc b/fpga_interchange/examples/wire/wire.xdc
index e1fce5f0..c923f0fc 100644
--- a/fpga_interchange/examples/wire/wire.xdc
+++ b/fpga_interchange/examples/wire/wire.xdc
@@ -1,2 +1,5 @@
 set_property PACKAGE_PIN N16 [get_ports i]
 set_property PACKAGE_PIN N15 [get_ports o]
+
+set_property IOSTANDARD LVCMOS33 [get_ports i]
+set_property IOSTANDARD LVCMOS33 [get_ports o]
-- 
cgit v1.2.3