From 0426ba4e877c0ec1130d8ab7bc74e70cc4e406bf Mon Sep 17 00:00:00 2001 From: gatecat Date: Tue, 1 Jun 2021 08:57:46 +0100 Subject: interchange: Add LIFCL-40 EVN tests Signed-off-by: gatecat --- fpga_interchange/examples/devices/LIFCL-40/test_data.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 fpga_interchange/examples/devices/LIFCL-40/test_data.yaml (limited to 'fpga_interchange/examples/devices/LIFCL-40/test_data.yaml') diff --git a/fpga_interchange/examples/devices/LIFCL-40/test_data.yaml b/fpga_interchange/examples/devices/LIFCL-40/test_data.yaml new file mode 100644 index 00000000..c4787eba --- /dev/null +++ b/fpga_interchange/examples/devices/LIFCL-40/test_data.yaml @@ -0,0 +1,8 @@ +pip_test: + - src_wire: R3C3_PLC.PLC/JDI0_SLICEA + dst_wire: R3C3/JF0 +bel_pin_test: + - bel: R7C3_PLC.PLC/SLICEA_LUT0 + pin: D + wire: R7C3_PLC.PLC/JD0_SLICEA + -- cgit v1.2.3