From f64d06fa0287cede913942380ddf84c380b2e79b Mon Sep 17 00:00:00 2001 From: gatecat Date: Tue, 6 Jul 2021 10:13:50 +0100 Subject: interchange: Improve search for PAD-attached bels Signed-off-by: gatecat --- fpga_interchange/arch.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'fpga_interchange/arch.h') diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h index 6e77054f..b71b1d03 100644 --- a/fpga_interchange/arch.h +++ b/fpga_interchange/arch.h @@ -708,7 +708,8 @@ struct Arch : ArchAPI // ------------------------------------------------- - void place_iobufs(WireId pad_wire, NetInfo *net, const pool &tightly_attached_bels, + void place_iobufs(WireId pad_wire, NetInfo *net, + const dict &tightly_attached_bels, pool *placed_cells); void pack_ports(); -- cgit v1.2.3 From 31abefc8e49edce55fb42c99ac99b81e948d9004 Mon Sep 17 00:00:00 2001 From: gatecat Date: Tue, 6 Jul 2021 10:38:08 +0100 Subject: interchange: Allow pseudo pip wires to overlap with bound site wires on the same net Signed-off-by: gatecat --- fpga_interchange/arch.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'fpga_interchange/arch.h') diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h index b71b1d03..896a603a 100644 --- a/fpga_interchange/arch.h +++ b/fpga_interchange/arch.h @@ -576,7 +576,8 @@ struct Arch : ArchAPI const PipInfoPOD &pip_data = pip_info(chip_info, pip); for (int32_t wire_index : pip_data.pseudo_cell_wires) { wire.index = wire_index; - assign_net_to_wire(wire, net, "pseudo", /*require_empty=*/true); + if (getBoundWireNet(wire) != net) + assign_net_to_wire(wire, net, "pseudo", /*require_empty=*/true); } if (pip_data.pseudo_cell_wires.size() > 0) { -- cgit v1.2.3