From c8dccd3e7bec95c635ebe435c8454ffe10edd6f3 Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Thu, 25 Mar 2021 17:11:06 -0700
Subject: Implement debugging tools for site router.

 - Finishes implementation of SiteArch::nameOfPip and SiteArch::nameOfWire
 - Adds "explain_bel_status", which should be an exhaustive diagnostic
   of the status of a BEL placement.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 fpga_interchange/arch.cc | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

(limited to 'fpga_interchange/arch.cc')

diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index e6e784f7..09e539e2 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -1861,6 +1861,36 @@ void Arch::remove_site_routing()
     }
 }
 
+void Arch::explain_bel_status(BelId bel) const
+{
+    if (isBelLocationValid(bel)) {
+        log_info("BEL %s is valid!\n", nameOfBel(bel));
+        return;
+    }
+
+    auto iter = tileStatus.find(bel.tile);
+    NPNR_ASSERT(iter != tileStatus.end());
+    const TileStatus &tile_status = iter->second;
+    const CellInfo *cell = tile_status.boundcells[bel.index];
+    if (!dedicated_interconnect.isBelLocationValid(bel, cell)) {
+        dedicated_interconnect.explain_bel_status(bel, cell);
+        return;
+    }
+
+    if (io_port_types.count(cell->type)) {
+        return;
+    }
+
+    if (!is_cell_valid_constraints(cell, tile_status, /*explain_constraints=*/true)) {
+        return;
+    }
+
+    auto &bel_data = bel_info(chip_info, bel);
+    const SiteRouter &site = get_site_status(tile_status, bel_data);
+    NPNR_ASSERT(!site.checkSiteRouting(getCtx(), tile_status));
+    site.explain(getCtx());
+}
+
 // Instance constraint templates.
 template void Arch::ArchConstraints::bindBel(Arch::ArchConstraints::TagState *, const Arch::ConstraintRange);
 template void Arch::ArchConstraints::unbindBel(Arch::ArchConstraints::TagState *, const Arch::ConstraintRange);
-- 
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