From c11ad31393389e0a16d84c2934332ea3755de60c Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Thu, 1 Apr 2021 15:18:17 -0700
Subject: [interchange] Scale edge cost of pseudo pips.

Previous pseudo pips were the same cost as regular pips, but this is
definitely too fast, and meant that the router was prefering them.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 fpga_interchange/arch.cc | 11 +++++++++++
 1 file changed, 11 insertions(+)

(limited to 'fpga_interchange/arch.cc')

diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index 5b38a879..f9209922 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -1959,6 +1959,17 @@ void Arch::explain_bel_status(BelId bel) const
     site.explain(getCtx());
 }
 
+DelayQuad Arch::getPipDelay(PipId pip) const {
+    // FIXME: Implement when adding timing-driven place and route.
+    const auto & pip_data = pip_info(chip_info, pip);
+
+    // Scale pseudo-pips by the number of wires they consume to make them
+    // more expensive than a single edge.  This approximation exists soley to
+    // make the non-timing driven solution avoid thinking that pseudo-pips
+    // are the same cost as regular pips.
+    return DelayQuad(100*(1+pip_data.pseudo_cell_wires.size()));
+}
+
 // Instance constraint templates.
 template void Arch::ArchConstraints::bindBel(Arch::ArchConstraints::TagState *, const Arch::ConstraintRange);
 template void Arch::ArchConstraints::unbindBel(Arch::ArchConstraints::TagState *, const Arch::ConstraintRange);
-- 
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