From 8c468acff8900f40e909882cfbf9381a59199b79 Mon Sep 17 00:00:00 2001 From: Alessandro Comodi Date: Wed, 12 May 2021 18:25:47 +0200 Subject: interchange: site router: add valid pips list to check during routing Signed-off-by: Alessandro Comodi --- fpga_interchange/arch.cc | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) (limited to 'fpga_interchange/arch.cc') diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc index ad4d90e8..a05878f6 100644 --- a/fpga_interchange/arch.cc +++ b/fpga_interchange/arch.cc @@ -1776,15 +1776,15 @@ bool Arch::checkPipAvailForNet(PipId pip, NetInfo *net) const } } + auto tile_status_iter = tileStatus.find(pip.tile); + if (pip_data.pseudo_cell_wires.size() > 0) { // FIXME: This pseudo pip check is incomplete, because constraint // failures will not be detected. However the current FPGA // interchange schema does not provide a cell type to place. - auto iter = tileStatus.find(pip.tile); - if (iter != tileStatus.end()) { - if (!iter->second.pseudo_pip_model.checkPipAvail(getCtx(), pip)) { - return false; - } + if (tile_status_iter != tileStatus.end() && + !tile_status_iter->second.pseudo_pip_model.checkPipAvail(getCtx(), pip)) { + return false; } } @@ -1797,12 +1797,16 @@ bool Arch::checkPipAvailForNet(PipId pip, NetInfo *net) const bool valid_pip = false; if (pip.tile == net->driver.cell->bel.tile) { - const BelInfoPOD &bel_data = tile_type.bel_data[net->driver.cell->bel.index]; - if (bel_data.site == pip_data.site) { - // Only allow site pips or output site ports. - if (dst_wire_data.site == -1) { - // Allow output site port from this site. - NPNR_ASSERT(src_wire_data.site == pip_data.site); + if (tile_status_iter == tileStatus.end()) { + // there is no tile status and nothing blocks the validity of this PIP + valid_pip = true; + } else { + const BelInfoPOD &bel_data = tile_type.bel_data[net->driver.cell->bel.index]; + const SiteRouter &site_router = get_site_status(tile_status_iter->second, bel_data); + + const auto& pips = site_router.valid_pips; + auto result = std::find(pips.begin(), pips.end(), pip); + if (result != pips.end()) { valid_pip = true; } } -- cgit v1.2.3