From e9d5b75d1d9333d359e576508235c7e35002b1c8 Mon Sep 17 00:00:00 2001 From: gatecat Date: Thu, 10 Jun 2021 13:10:29 +0100 Subject: ecp5: Add missing clock edge assignments Signed-off-by: gatecat --- ecp5/arch.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'ecp5') diff --git a/ecp5/arch.cc b/ecp5/arch.cc index ae9d1af0..aed7cf20 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -1067,6 +1067,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port } } else if (cell->type == id_IOLOGIC || cell->type == id_SIOLOGIC) { info.clock_port = id_CLK; + info.edge = RISING_EDGE; if (cell->ports.at(port).type == PORT_OUT) { info.clockToQ = DelayQuad(getDelayFromNS(0.5)); } else { @@ -1075,6 +1076,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port } } else if (cell->type == id_DQSBUFM) { info.clock_port = id_SCLK; + info.edge = RISING_EDGE; if (port == id_DATAVALID) { info.clockToQ = DelayQuad(getDelayFromNS(0.2)); } else if (port == id_READ0 || port == id_READ1) { -- cgit v1.2.3