From cc746d888ba418db859a8acd3a3d3c4ddf48e294 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 15 Nov 2018 17:39:13 +0000 Subject: ecp5: Fix timing pip classes Signed-off-by: David Shah --- ecp5/trellis_import.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'ecp5') diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py index 82d51076..d9892a28 100755 --- a/ecp5/trellis_import.py +++ b/ecp5/trellis_import.py @@ -222,7 +222,7 @@ def write_database(dev_name, chip, ddrg, endianness): loc = loc_with_type[arc_loctype] lt = ddrg.typeAtLocation[pytrellis.Location(loc[0] + rel.x, loc[1] + rel.y)] wire = ddrg.locationTypes[lt].wires[idx] - return "R{}C{}_{}".format(loc[0] + rel.x, loc[1] + rel.y, ddrg.to_str(wire.name)) + return "R{}C{}_{}".format(loc[1] + rel.y, loc[0] + rel.x, ddrg.to_str(wire.name)) bba = BinaryBlobAssembler() bba.pre('#include "nextpnr.h"') -- cgit v1.2.3