From f61e9e56094946492bdd364ab272c19919a9faca Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 24 Jul 2018 12:22:57 +0200 Subject: ecp5: Set BANKREF to correct VccIO Signed-off-by: David Shah --- ecp5/bitstream.cc | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) (limited to 'ecp5/bitstream.cc') diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index 19ddb9f9..1efee5fc 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -30,6 +30,7 @@ #include #include +#include "io.h" #include "log.h" #include "util.h" @@ -182,12 +183,34 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex } } } + // Find bank voltages + std::unordered_map bankVcc; + for (auto &cell : ctx->cells) { + CellInfo *ci = cell.second.get(); + if (ci->bel != BelId() && ci->type == ctx->id("TRELLIS_IO")) { + int bank = ctx->getPioBelBank(ci->bel); + std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33"); + IOVoltage vcc = get_vccio(ioType_from_str(iotype)); + if (bankVcc.find(bank) != bankVcc.end()) { + // TODO: strong and weak constraints + if (bankVcc[bank] != vcc) { + log_error("Error processing '%s': incompatible IO voltages %s and %s on bank %d.", + cell.first.c_str(ctx), iovoltage_to_str(bankVcc[bank]).c_str(), + iovoltage_to_str(vcc).c_str(), bank); + } + } else { + bankVcc[bank] = vcc; + } + } + } - // Set all bankref tiles to 3.3V (TODO) + // Set all bankref tiles to appropriate VccIO for (const auto &tile : empty_chip.tiles) { std::string type = tile.second->info.type; if (type.find("BANKREF") != std::string::npos && type != "BANKREF8") { - cc.tiles[tile.first].add_enum("BANK.VCCIO", "3V3"); + int bank = std::stoi(type.substr(7)); + if (bankVcc.find(bank) != bankVcc.end()) + cc.tiles[tile.first].add_enum("BANK.VCCIO", iovoltage_to_str(bankVcc[bank])); } } -- cgit v1.2.3 From 35a6bc496eb28f26c42e25a5e746987329e96f3e Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 24 Jul 2018 12:57:54 +0200 Subject: ecp5: Support for differential IO Signed-off-by: David Shah --- ecp5/bitstream.cc | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'ecp5/bitstream.cc') diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index 1efee5fc..c2218762 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -258,6 +258,20 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex std::string pic_tile = get_pic_tile(ctx, empty_chip, bel); cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype); cc.tiles[pic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype); + if (is_differential(ioType_from_str(iotype))) { + // Explicitly disable other pair + std::string other; + if (pio == "PIOA") + other = "PIOB"; + else if (pio == "PIOC") + other = "PIOD"; + else + log_error("cannot place differential IO at location %s\n", pio.c_str()); + cc.tiles[pio_tile].add_enum(other + ".BASE_TYPE", "_NONE_"); + cc.tiles[pic_tile].add_enum(other + ".BASE_TYPE", "_NONE_"); + cc.tiles[pio_tile].add_enum(other + ".PULLMODE", "NONE"); + cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE"); + } if (dir != "INPUT" && (ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr)) { // Tie tristate low if unconnected for outputs or bidir @@ -270,7 +284,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex std::string cib_wirename = ctx->locInfo(cib_wire)->wire_data[cib_wire.index].name.get(); cc.tiles[cib_tile].add_enum("CIB." + cib_wirename + "MUX", "0"); } - if (dir == "INPUT") { + if (dir == "INPUT" && !is_differential(ioType_from_str(iotype))) { cc.tiles[pio_tile].add_enum(pio + ".HYSTERESIS", "ON"); } } else { -- cgit v1.2.3 From 6a7f3cd336ebb35389d0c4ee4f8b457d2a2e026a Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 24 Jul 2018 21:25:33 +0200 Subject: ecp5: Working on LVDS inputs for Versa support Signed-off-by: David Shah --- ecp5/bitstream.cc | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'ecp5/bitstream.cc') diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index c2218762..9a925d63 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -185,6 +185,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex } // Find bank voltages std::unordered_map bankVcc; + std::unordered_map bankLvds; + for (auto &cell : ctx->cells) { CellInfo *ci = cell.second.get(); if (ci->bel != BelId() && ci->type == ctx->id("TRELLIS_IO")) { @@ -201,6 +203,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex } else { bankVcc[bank] = vcc; } + if (iotype == "LVDS") + bankLvds[bank] = true; } } @@ -211,6 +215,10 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex int bank = std::stoi(type.substr(7)); if (bankVcc.find(bank) != bankVcc.end()) cc.tiles[tile.first].add_enum("BANK.VCCIO", iovoltage_to_str(bankVcc[bank])); + if (bankLvds[bank]) { + cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON"); + cc.tiles[tile.first].add_enum("BANK.LVDSO", "ON"); + } } } -- cgit v1.2.3 From 32c7247785f48b2307e559a0af50d9387bda8b49 Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 24 Jul 2018 22:26:26 +0200 Subject: ecp5: Bitsream gen tuning Signed-off-by: David Shah --- ecp5/bitstream.cc | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) (limited to 'ecp5/bitstream.cc') diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index 9a925d63..f1feba24 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -191,18 +191,23 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex CellInfo *ci = cell.second.get(); if (ci->bel != BelId() && ci->type == ctx->id("TRELLIS_IO")) { int bank = ctx->getPioBelBank(ci->bel); + std::string dir = str_or_default(ci->params, ctx->id("DIR"), "INPUT"); std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33"); - IOVoltage vcc = get_vccio(ioType_from_str(iotype)); - if (bankVcc.find(bank) != bankVcc.end()) { - // TODO: strong and weak constraints - if (bankVcc[bank] != vcc) { - log_error("Error processing '%s': incompatible IO voltages %s and %s on bank %d.", - cell.first.c_str(ctx), iovoltage_to_str(bankVcc[bank]).c_str(), - iovoltage_to_str(vcc).c_str(), bank); + + if (dir != "INPUT") { + IOVoltage vcc = get_vccio(ioType_from_str(iotype)); + if (bankVcc.find(bank) != bankVcc.end()) { + // TODO: strong and weak constraints + if (bankVcc[bank] != vcc) { + log_error("Error processing '%s': incompatible IO voltages %s and %s on bank %d.", + cell.first.c_str(ctx), iovoltage_to_str(bankVcc[bank]).c_str(), + iovoltage_to_str(vcc).c_str(), bank); + } + } else { + bankVcc[bank] = vcc; } - } else { - bankVcc[bank] = vcc; } + if (iotype == "LVDS") bankLvds[bank] = true; } @@ -275,8 +280,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex other = "PIOD"; else log_error("cannot place differential IO at location %s\n", pio.c_str()); - cc.tiles[pio_tile].add_enum(other + ".BASE_TYPE", "_NONE_"); - cc.tiles[pic_tile].add_enum(other + ".BASE_TYPE", "_NONE_"); + //cc.tiles[pio_tile].add_enum(other + ".BASE_TYPE", "_NONE_"); + //cc.tiles[pic_tile].add_enum(other + ".BASE_TYPE", "_NONE_"); cc.tiles[pio_tile].add_enum(other + ".PULLMODE", "NONE"); cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE"); } -- cgit v1.2.3 From 7a8e8999d21205044e707a2765dc444531d69cef Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 25 Jul 2018 19:45:38 +0200 Subject: clangformat Signed-off-by: David Shah --- ecp5/bitstream.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'ecp5/bitstream.cc') diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index f1feba24..f87b7038 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -280,8 +280,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex other = "PIOD"; else log_error("cannot place differential IO at location %s\n", pio.c_str()); - //cc.tiles[pio_tile].add_enum(other + ".BASE_TYPE", "_NONE_"); - //cc.tiles[pic_tile].add_enum(other + ".BASE_TYPE", "_NONE_"); + // cc.tiles[pio_tile].add_enum(other + ".BASE_TYPE", "_NONE_"); + // cc.tiles[pic_tile].add_enum(other + ".BASE_TYPE", "_NONE_"); cc.tiles[pio_tile].add_enum(other + ".PULLMODE", "NONE"); cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE"); } -- cgit v1.2.3 From 8db19778a09954e7c0b4803bdfc40509de0403fd Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 26 Jul 2018 18:48:07 +0200 Subject: Fix name clash for ecp5 --- ecp5/bitstream.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'ecp5/bitstream.cc') diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index f87b7038..df9b12d5 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -174,7 +174,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex // Add all set, configurable pips to the config for (auto pip : ctx->getPips()) { if (ctx->getBoundPipNet(pip) != IdString()) { - if (ctx->getPipType(pip) == 0) { // ignore fixed pips + if (ctx->getPipClass(pip) == 0) { // ignore fixed pips std::string tile = empty_chip.get_tile_by_position_and_type(pip.location.y, pip.location.x, ctx->getPipTiletype(pip)); std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip)); -- cgit v1.2.3