From bad926bcc3e4d77bcb76d54eff689a91233c71fb Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 9 Jul 2018 12:02:31 +0200 Subject: ecp5: Adding bitstream gen for pips and LUT init Signed-off-by: David Shah --- ecp5/bitstream.cc | 135 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 135 insertions(+) create mode 100644 ecp5/bitstream.cc (limited to 'ecp5/bitstream.cc') diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc new file mode 100644 index 00000000..e44892ed --- /dev/null +++ b/ecp5/bitstream.cc @@ -0,0 +1,135 @@ +/* + * nextpnr -- Next Generation Place and Route + * + * Copyright (C) 2018 David Shah + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "bitstream.h" + +// From Project Trellis +#include "BitDatabase.hpp" +#include "Bitstream.hpp" +#include "Chip.hpp" +#include "ChipConfig.hpp" +#include "Tile.hpp" +#include "TileConfig.hpp" + +#include +#include + +#include "log.h" +#include "util.h" + +NEXTPNR_NAMESPACE_BEGIN + +// Convert an absolute wire name to a relative Trellis one +static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire) +{ + std::string basename = ctx->locInfo(wire)->wire_data[wire.index].name.get(); + std::string prefix2 = basename.substr(0, 2); + if (prefix2 == "G_" || prefix2 == "L_" || prefix2 == "R_") + return basename; + if (loc == wire.location) + return basename; + std::string rel_prefix; + if (wire.location.y < loc.y) + rel_prefix += "N" + to_string(loc.y - wire.location.y); + if (wire.location.y > loc.y) + rel_prefix += "S" + to_string(wire.location.y - loc.y); + if (wire.location.x > loc.x) + rel_prefix += "E" + to_string(wire.location.x - loc.x); + if (wire.location.x < loc.x) + rel_prefix += "W" + to_string(loc.x - wire.location.x); + return rel_prefix + "_" + basename; +} + +static std::vector int_to_bitvector(int val, int size) +{ + std::vector bv; + for (int i = 0; i < size; i++) { + bv.push_back((val & (1 << i)) != 0); + } + return bv; +} + +void write_bitstream(Context *ctx, std::string base_config_file, std::string text_config_file, + std::string bitstream_file) +{ + Trellis::Chip empty_chip(ctx->getChipName()); + Trellis::ChipConfig cc; + if (!base_config_file.empty()) { + std::ifstream config_file(base_config_file); + if (!config_file) { + log_error("failed to open base config file '%s'\n", base_config_file.c_str()); + } + std::string str((std::istreambuf_iterator(config_file)), std::istreambuf_iterator()); + cc = Trellis::ChipConfig::from_string(str); + } else { + cc.chip_name = ctx->getChipName(); + // TODO: .bit metadata + } + + // Add all set, configurable pips to the config + for (auto pip : ctx->getPips()) { + if (ctx->getBoundPipNet(pip) != IdString()) { + if (ctx->getPipType(pip) == 0) { // ignore fixed pips + auto tile = empty_chip.get_tile_by_position_and_type(pip.location.y, pip.location.x, + ctx->getPipTiletype(pip)); + std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip)); + std::string sink = get_trellis_wirename(ctx, pip.location, ctx->getPipDstWire(pip)); + cc.tiles[tile->info.name].add_arc(sink, source); + } + } + } + + // Set all bankref tiles to 3.3V (TODO) + for (const auto &tile : empty_chip.tiles) { + std::string type = tile.second->info.type; + if (type.find("BANKREF") != std::string::npos && type != "BANKREF8") { + cc.tiles[type].add_enum("BANK.VCCIO", "3V3"); + } + } + + // Configure slices + for (auto &cell : ctx->cells) { + CellInfo *ci = cell.second.get(); + if (ci->bel == BelId()) { + log_warning("found unplaced cell '%s' during bitstream gen\n", ci->name.c_str(ctx)); + } + BelId bel = ci->bel; + if (ci->type == ctx->id("TRELLIS_SLICE")) { + auto tile = empty_chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, "PLC2"); + std::string tname = tile->info.name; + std::string slice = ctx->locInfo(bel)->bel_data[bel.index].name.get(); + int lut0_init = int_or_default(ci->params, ctx->id("LUT0_INITVAL")); + int lut1_init = int_or_default(ci->params, ctx->id("LUT1_INITVAL")); + cc.tiles[tname].add_word(slice + ".K0.INIT", int_to_bitvector(lut0_init, 16)); + cc.tiles[tname].add_word(slice + ".K1.INIT", int_to_bitvector(lut1_init, 16)); + } + } + + // Configure chip + Trellis::Chip cfg_chip = cc.to_chip(); + if (!bitstream_file.empty()) { + Trellis::Bitstream::serialise_chip(cfg_chip).write_bit_py(bitstream_file); + } + if (!text_config_file.empty()) { + std::ofstream out_config(text_config_file); + out_config << cc.to_string(); + } +} + +NEXTPNR_NAMESPACE_END -- cgit v1.2.3 From b397dd80712005e4c71b492e27d6af35e6bdc1e9 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 9 Jul 2018 12:55:56 +0200 Subject: ecp5: Adding bitstream gen for slice config Signed-off-by: David Shah --- ecp5/bitstream.cc | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'ecp5/bitstream.cc') diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index e44892ed..5f9294c2 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -118,6 +118,20 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex int lut1_init = int_or_default(ci->params, ctx->id("LUT1_INITVAL")); cc.tiles[tname].add_word(slice + ".K0.INIT", int_to_bitvector(lut0_init, 16)); cc.tiles[tname].add_word(slice + ".K1.INIT", int_to_bitvector(lut1_init, 16)); + cc.tiles[tname].add_enum(slice + ".MODE", str_or_default(ci->params, ctx->id("MODE"), "LOGIC")); + cc.tiles[tname].add_enum(slice + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "ENABLED")); + cc.tiles[tname].add_enum(slice + ".REG0.SD", str_or_default(ci->params, ctx->id("REG0_SD"), "0")); + cc.tiles[tname].add_enum(slice + ".REG1.SD", str_or_default(ci->params, ctx->id("REG1_SD"), "0")); + cc.tiles[tname].add_enum(slice + ".REG0.REGSET", + str_or_default(ci->params, ctx->id("REG0_REGSET"), "RESET")); + cc.tiles[tname].add_enum(slice + ".REG1.REGSET", + str_or_default(ci->params, ctx->id("REG1_REGSET"), "RESET")); + cc.tiles[tname].add_enum(slice + ".CEMUX", str_or_default(ci->params, ctx->id("CEMUX"), "1")); + // TODO: CLKMUX, CEMUX, carry + } else if (ci->type == ctx->id("TRELLIS_IO")) { + // TODO: IO config + } else { + NPNR_ASSERT_FALSE("unsupported cell type"); } } -- cgit v1.2.3 From 29d65bd368fa32f7ea13515902df752d30ec4f39 Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 10 Jul 2018 11:24:30 +0200 Subject: ecp5: Working on bitstream gen Signed-off-by: David Shah --- ecp5/bitstream.cc | 106 +++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 105 insertions(+), 1 deletion(-) (limited to 'ecp5/bitstream.cc') diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index 5f9294c2..04bbc24f 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -33,6 +33,8 @@ #include "log.h" #include "util.h" +#define fmt_str(x) (static_cast(std::ostringstream() << x).str()) + NEXTPNR_NAMESPACE_BEGIN // Convert an absolute wire name to a relative Trellis one @@ -65,11 +67,97 @@ static std::vector int_to_bitvector(int val, int size) return bv; } +// Get the PIO tile corresponding to a PIO bel +static std::string get_pio_tile(Context *ctx, Trellis::Chip &chip, BelId bel) +{ + static const std::set pioabcd_l = {"PICL1", "PICL1_DQS0", "PICL1_DQS3"}; + static const std::set pioabcd_r = {"PICR1", "PICR1_DQS0", "PICR1_DQS3"}; + static const std::set pioa_b = {"PICB0", "EFB0_PICB0", "EFB2_PICB0"}; + static const std::set piob_b = {"PICB1", "EFB1_PICB1", "EFB3_PICB1"}; + + std::string pio_name = ctx->locInfo(bel)->bel_data[bel.index].name.get(); + if (bel.location.y == 0) { + if (pio_name == "PIOA") { + return chip.get_tile_by_position_and_type(0, bel.location.x, "PIOT0")->info.name; + } else if (pio_name == "PIOB") { + return chip.get_tile_by_position_and_type(0, bel.location.x + 1, "PIOT1")->info.name; + } else { + NPNR_ASSERT_FALSE("bad PIO location"); + } + } else if (bel.location.y == ctx->chip_info->height - 1) { + if (pio_name == "PIOA") { + return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, pioa_b)->info.name; + } else if (pio_name == "PIOB") { + return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x + 1, piob_b)->info.name; + } else { + NPNR_ASSERT_FALSE("bad PIO location"); + } + } else if (bel.location.x == 0) { + return chip.get_tile_by_position_and_type(bel.location.y + 1, bel.location.x, pioabcd_l)->info.name; + } else if (bel.location.x == ctx->chip_info->width - 1) { + return chip.get_tile_by_position_and_type(bel.location.y + 1, bel.location.x, pioabcd_r)->info.name; + } else { + NPNR_ASSERT_FALSE("bad PIO location"); + } +} + +// Get the PIC tile corresponding to a PIO bel +static std::string get_pic_tile(Context *ctx, Trellis::Chip &chip, BelId bel) +{ + static const std::set picab_l = {"PICL0", "PICL0_DQS2"}; + static const std::set piccd_l = {"PICL2", "PICL2_DQS1", "MIB_CIB_LR"}; + static const std::set picab_r = {"PICR0", "PICR0_DQS2"}; + static const std::set piccd_r = {"PICR2", "PICR2_DQS1", "MIB_CIB_LR_A"}; + + static const std::set pica_b = {"PICB0", "EFB0_PICB0", "EFB2_PICB0"}; + static const std::set picb_b = {"PICB1", "EFB1_PICB1", "EFB3_PICB1"}; + + std::string pio_name = ctx->locInfo(bel)->bel_data[bel.index].name.get(); + if (bel.location.y == 0) { + if (pio_name == "PIOA") { + return chip.get_tile_by_position_and_type(1, bel.location.x, "PICT0")->info.name; + } else if (pio_name == "PIOB") { + return chip.get_tile_by_position_and_type(1, bel.location.x + 1, "PICT1")->info.name; + } else { + NPNR_ASSERT_FALSE("bad PIO location"); + } + } else if (bel.location.y == ctx->chip_info->height - 1) { + if (pio_name == "PIOA") { + return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, pica_b)->info.name; + } else if (pio_name == "PIOB") { + return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x + 1, picb_b)->info.name; + } else { + NPNR_ASSERT_FALSE("bad PIO location"); + } + } else if (bel.location.x == 0) { + if (pio_name == "PIOA" || pio_name == "PIOB") { + return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, picab_l)->info.name; + } else if (pio_name == "PIOC" || pio_name == "PIOD") { + return chip.get_tile_by_position_and_type(bel.location.y + 2, bel.location.x, piccd_l)->info.name; + } else { + NPNR_ASSERT_FALSE("bad PIO location"); + } + } else if (bel.location.x == ctx->chip_info->width - 1) { + if (pio_name == "PIOA" || pio_name == "PIOB") { + return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, picab_r)->info.name; + } else if (pio_name == "PIOC" || pio_name == "PIOD") { + return chip.get_tile_by_position_and_type(bel.location.y + 2, bel.location.x, piccd_r)->info.name; + } else { + NPNR_ASSERT_FALSE("bad PIO location"); + } + } else { + NPNR_ASSERT_FALSE("bad PIO location"); + } +} + void write_bitstream(Context *ctx, std::string base_config_file, std::string text_config_file, std::string bitstream_file) { Trellis::Chip empty_chip(ctx->getChipName()); Trellis::ChipConfig cc; + + std::set cib_tiles = {"CIB", "CIB_LR", "CIB_LR_S", "CIB_EFB0", "CIB_EFB1"}; + if (!base_config_file.empty()) { std::ifstream config_file(base_config_file); if (!config_file) { @@ -129,7 +217,23 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex cc.tiles[tname].add_enum(slice + ".CEMUX", str_or_default(ci->params, ctx->id("CEMUX"), "1")); // TODO: CLKMUX, CEMUX, carry } else if (ci->type == ctx->id("TRELLIS_IO")) { - // TODO: IO config + std::string pio = ctx->locInfo(bel)->bel_data[bel.index].name.get(); + std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33"); + std::string dir = str_or_default(ci->params, ctx->id("DIR"), "INPUT"); + std::string pio_tile = get_pio_tile(ctx, empty_chip, bel); + std::string pic_tile = get_pic_tile(ctx, empty_chip, bel); + cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype); + cc.tiles[pic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype); + if (dir != "INPUT" && (ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr)) { + // Tie tristate low if unconnected for outputs or bidir + std::string jpt = fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/JPADDT" << pio.back()); + WireId jpt_wire = ctx->getWireByName(ctx->id(jpt)); + PipId jpt_pip = *ctx->getPipsUphill(jpt_wire).begin(); + WireId cib_wire = ctx->getPipSrcWire(jpt_pip); + std::string cib_tile = empty_chip.get_tile_by_position_and_type(cib_wire.location.y, cib_wire.location.x, cib_tiles)->info.name; + std::string cib_wirename = ctx->locInfo(cib_wire)->wire_data[cib_wire.index].name.get(); + cc.tiles[cib_tile].add_enum("CIB." + cib_wirename + "MUX", "0"); + } } else { NPNR_ASSERT_FALSE("unsupported cell type"); } -- cgit v1.2.3 From 98cdb6082d1f916bd47676c3e7f1feab6b585216 Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 10 Jul 2018 11:57:58 +0200 Subject: ecp5: Bitstream progress Signed-off-by: David Shah --- ecp5/bitstream.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'ecp5/bitstream.cc') diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index 04bbc24f..f4f175bb 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -187,7 +187,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex for (const auto &tile : empty_chip.tiles) { std::string type = tile.second->info.type; if (type.find("BANKREF") != std::string::npos && type != "BANKREF8") { - cc.tiles[type].add_enum("BANK.VCCIO", "3V3"); + cc.tiles[tile.first].add_enum("BANK.VCCIO", "3V3"); } } -- cgit v1.2.3 From 1830c9372e9bb959cb886c8271d64778550a7ebb Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 10 Jul 2018 12:31:58 +0200 Subject: ecp5: *** Blinky working *** Signed-off-by: David Shah --- ecp5/bitstream.cc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'ecp5/bitstream.cc') diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index f4f175bb..0e8d4aa4 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -234,6 +234,9 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex std::string cib_wirename = ctx->locInfo(cib_wire)->wire_data[cib_wire.index].name.get(); cc.tiles[cib_tile].add_enum("CIB." + cib_wirename + "MUX", "0"); } + if (dir == "INPUT") { + cc.tiles[pio_tile].add_enum(pio + ".HYSTERESIS", "ON"); + } } else { NPNR_ASSERT_FALSE("unsupported cell type"); } -- cgit v1.2.3 From bcc63091fb30ac15c9f98bfc3b3a41d921af0bd4 Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 11 Jul 2018 11:08:12 +0200 Subject: ecp5: New libtrellis tile lookup API Signed-off-by: David Shah --- ecp5/bitstream.cc | 37 ++++++++++++++++++------------------- 1 file changed, 18 insertions(+), 19 deletions(-) (limited to 'ecp5/bitstream.cc') diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index 0e8d4aa4..a04a4250 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -78,24 +78,24 @@ static std::string get_pio_tile(Context *ctx, Trellis::Chip &chip, BelId bel) std::string pio_name = ctx->locInfo(bel)->bel_data[bel.index].name.get(); if (bel.location.y == 0) { if (pio_name == "PIOA") { - return chip.get_tile_by_position_and_type(0, bel.location.x, "PIOT0")->info.name; + return chip.get_tile_by_position_and_type(0, bel.location.x, "PIOT0"); } else if (pio_name == "PIOB") { - return chip.get_tile_by_position_and_type(0, bel.location.x + 1, "PIOT1")->info.name; + return chip.get_tile_by_position_and_type(0, bel.location.x + 1, "PIOT1"); } else { NPNR_ASSERT_FALSE("bad PIO location"); } } else if (bel.location.y == ctx->chip_info->height - 1) { if (pio_name == "PIOA") { - return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, pioa_b)->info.name; + return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, pioa_b); } else if (pio_name == "PIOB") { - return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x + 1, piob_b)->info.name; + return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x + 1, piob_b); } else { NPNR_ASSERT_FALSE("bad PIO location"); } } else if (bel.location.x == 0) { - return chip.get_tile_by_position_and_type(bel.location.y + 1, bel.location.x, pioabcd_l)->info.name; + return chip.get_tile_by_position_and_type(bel.location.y + 1, bel.location.x, pioabcd_l); } else if (bel.location.x == ctx->chip_info->width - 1) { - return chip.get_tile_by_position_and_type(bel.location.y + 1, bel.location.x, pioabcd_r)->info.name; + return chip.get_tile_by_position_and_type(bel.location.y + 1, bel.location.x, pioabcd_r); } else { NPNR_ASSERT_FALSE("bad PIO location"); } @@ -115,33 +115,33 @@ static std::string get_pic_tile(Context *ctx, Trellis::Chip &chip, BelId bel) std::string pio_name = ctx->locInfo(bel)->bel_data[bel.index].name.get(); if (bel.location.y == 0) { if (pio_name == "PIOA") { - return chip.get_tile_by_position_and_type(1, bel.location.x, "PICT0")->info.name; + return chip.get_tile_by_position_and_type(1, bel.location.x, "PICT0"); } else if (pio_name == "PIOB") { - return chip.get_tile_by_position_and_type(1, bel.location.x + 1, "PICT1")->info.name; + return chip.get_tile_by_position_and_type(1, bel.location.x + 1, "PICT1"); } else { NPNR_ASSERT_FALSE("bad PIO location"); } } else if (bel.location.y == ctx->chip_info->height - 1) { if (pio_name == "PIOA") { - return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, pica_b)->info.name; + return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, pica_b); } else if (pio_name == "PIOB") { - return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x + 1, picb_b)->info.name; + return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x + 1, picb_b); } else { NPNR_ASSERT_FALSE("bad PIO location"); } } else if (bel.location.x == 0) { if (pio_name == "PIOA" || pio_name == "PIOB") { - return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, picab_l)->info.name; + return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, picab_l); } else if (pio_name == "PIOC" || pio_name == "PIOD") { - return chip.get_tile_by_position_and_type(bel.location.y + 2, bel.location.x, piccd_l)->info.name; + return chip.get_tile_by_position_and_type(bel.location.y + 2, bel.location.x, piccd_l); } else { NPNR_ASSERT_FALSE("bad PIO location"); } } else if (bel.location.x == ctx->chip_info->width - 1) { if (pio_name == "PIOA" || pio_name == "PIOB") { - return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, picab_r)->info.name; + return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, picab_r); } else if (pio_name == "PIOC" || pio_name == "PIOD") { - return chip.get_tile_by_position_and_type(bel.location.y + 2, bel.location.x, piccd_r)->info.name; + return chip.get_tile_by_position_and_type(bel.location.y + 2, bel.location.x, piccd_r); } else { NPNR_ASSERT_FALSE("bad PIO location"); } @@ -174,11 +174,11 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex for (auto pip : ctx->getPips()) { if (ctx->getBoundPipNet(pip) != IdString()) { if (ctx->getPipType(pip) == 0) { // ignore fixed pips - auto tile = empty_chip.get_tile_by_position_and_type(pip.location.y, pip.location.x, + std::string tile = empty_chip.get_tile_by_position_and_type(pip.location.y, pip.location.x, ctx->getPipTiletype(pip)); std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip)); std::string sink = get_trellis_wirename(ctx, pip.location, ctx->getPipDstWire(pip)); - cc.tiles[tile->info.name].add_arc(sink, source); + cc.tiles[tile].add_arc(sink, source); } } } @@ -199,8 +199,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex } BelId bel = ci->bel; if (ci->type == ctx->id("TRELLIS_SLICE")) { - auto tile = empty_chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, "PLC2"); - std::string tname = tile->info.name; + std::string tname = empty_chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, "PLC2"); std::string slice = ctx->locInfo(bel)->bel_data[bel.index].name.get(); int lut0_init = int_or_default(ci->params, ctx->id("LUT0_INITVAL")); int lut1_init = int_or_default(ci->params, ctx->id("LUT1_INITVAL")); @@ -230,7 +229,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex WireId jpt_wire = ctx->getWireByName(ctx->id(jpt)); PipId jpt_pip = *ctx->getPipsUphill(jpt_wire).begin(); WireId cib_wire = ctx->getPipSrcWire(jpt_pip); - std::string cib_tile = empty_chip.get_tile_by_position_and_type(cib_wire.location.y, cib_wire.location.x, cib_tiles)->info.name; + std::string cib_tile = empty_chip.get_tile_by_position_and_type(cib_wire.location.y, cib_wire.location.x, cib_tiles); std::string cib_wirename = ctx->locInfo(cib_wire)->wire_data[cib_wire.index].name.get(); cc.tiles[cib_tile].add_enum("CIB." + cib_wirename + "MUX", "0"); } -- cgit v1.2.3 From 35216298d5538c0121ae98399518e8c82b7f7577 Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 11 Jul 2018 14:27:15 +0200 Subject: ecp5: Update arch to use new graphics API Signed-off-by: David Shah --- ecp5/bitstream.cc | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'ecp5/bitstream.cc') diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index a04a4250..e70d6bb2 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -33,7 +33,7 @@ #include "log.h" #include "util.h" -#define fmt_str(x) (static_cast(std::ostringstream() << x).str()) +#define fmt_str(x) (static_cast(std::ostringstream() << x).str()) NEXTPNR_NAMESPACE_BEGIN @@ -175,7 +175,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex if (ctx->getBoundPipNet(pip) != IdString()) { if (ctx->getPipType(pip) == 0) { // ignore fixed pips std::string tile = empty_chip.get_tile_by_position_and_type(pip.location.y, pip.location.x, - ctx->getPipTiletype(pip)); + ctx->getPipTiletype(pip)); std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip)); std::string sink = get_trellis_wirename(ctx, pip.location, ctx->getPipDstWire(pip)); cc.tiles[tile].add_arc(sink, source); @@ -223,13 +223,15 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex std::string pic_tile = get_pic_tile(ctx, empty_chip, bel); cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype); cc.tiles[pic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype); - if (dir != "INPUT" && (ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr)) { + if (dir != "INPUT" && + (ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr)) { // Tie tristate low if unconnected for outputs or bidir std::string jpt = fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/JPADDT" << pio.back()); WireId jpt_wire = ctx->getWireByName(ctx->id(jpt)); PipId jpt_pip = *ctx->getPipsUphill(jpt_wire).begin(); WireId cib_wire = ctx->getPipSrcWire(jpt_pip); - std::string cib_tile = empty_chip.get_tile_by_position_and_type(cib_wire.location.y, cib_wire.location.x, cib_tiles); + std::string cib_tile = + empty_chip.get_tile_by_position_and_type(cib_wire.location.y, cib_wire.location.x, cib_tiles); std::string cib_wirename = ctx->locInfo(cib_wire)->wire_data[cib_wire.index].name.get(); cc.tiles[cib_tile].add_enum("CIB." + cib_wirename + "MUX", "0"); } -- cgit v1.2.3 From 3352ff4abbcac563e08d78ed8aa77728d00284a8 Mon Sep 17 00:00:00 2001 From: Sergiusz Bazanski Date: Sat, 14 Jul 2018 11:46:32 +0100 Subject: Move read methods to ReadMethods, remove some legacy access to Arch --- ecp5/bitstream.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'ecp5/bitstream.cc') diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index e70d6bb2..b2376391 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -155,6 +155,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex { Trellis::Chip empty_chip(ctx->getChipName()); Trellis::ChipConfig cc; + auto &&proxy = ctx->rproxy(); std::set cib_tiles = {"CIB", "CIB_LR", "CIB_LR_S", "CIB_EFB0", "CIB_EFB1"}; @@ -172,7 +173,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex // Add all set, configurable pips to the config for (auto pip : ctx->getPips()) { - if (ctx->getBoundPipNet(pip) != IdString()) { + if (proxy.getBoundPipNet(pip) != IdString()) { if (ctx->getPipType(pip) == 0) { // ignore fixed pips std::string tile = empty_chip.get_tile_by_position_and_type(pip.location.y, pip.location.x, ctx->getPipTiletype(pip)); @@ -227,7 +228,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex (ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr)) { // Tie tristate low if unconnected for outputs or bidir std::string jpt = fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/JPADDT" << pio.back()); - WireId jpt_wire = ctx->getWireByName(ctx->id(jpt)); + WireId jpt_wire = proxy.getWireByName(ctx->id(jpt)); PipId jpt_pip = *ctx->getPipsUphill(jpt_wire).begin(); WireId cib_wire = ctx->getPipSrcWire(jpt_pip); std::string cib_tile = -- cgit v1.2.3 From ade67ecf21c274c73c99543e51eda99ac847686c Mon Sep 17 00:00:00 2001 From: Sergiusz Bazanski Date: Sat, 14 Jul 2018 18:50:23 +0100 Subject: Revert "Move read methods to ReadMethods, remove some legacy access to Arch" This reverts commit 3352ff4abbcac563e08d78ed8aa77728d00284a8. --- ecp5/bitstream.cc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'ecp5/bitstream.cc') diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index b2376391..e70d6bb2 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -155,7 +155,6 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex { Trellis::Chip empty_chip(ctx->getChipName()); Trellis::ChipConfig cc; - auto &&proxy = ctx->rproxy(); std::set cib_tiles = {"CIB", "CIB_LR", "CIB_LR_S", "CIB_EFB0", "CIB_EFB1"}; @@ -173,7 +172,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex // Add all set, configurable pips to the config for (auto pip : ctx->getPips()) { - if (proxy.getBoundPipNet(pip) != IdString()) { + if (ctx->getBoundPipNet(pip) != IdString()) { if (ctx->getPipType(pip) == 0) { // ignore fixed pips std::string tile = empty_chip.get_tile_by_position_and_type(pip.location.y, pip.location.x, ctx->getPipTiletype(pip)); @@ -228,7 +227,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex (ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr)) { // Tie tristate low if unconnected for outputs or bidir std::string jpt = fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/JPADDT" << pio.back()); - WireId jpt_wire = proxy.getWireByName(ctx->id(jpt)); + WireId jpt_wire = ctx->getWireByName(ctx->id(jpt)); PipId jpt_pip = *ctx->getPipsUphill(jpt_wire).begin(); WireId cib_wire = ctx->getPipSrcWire(jpt_pip); std::string cib_tile = -- cgit v1.2.3