From 998d055ea7f8bcc423d2aa2d75f5f27b6368666e Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 13 Dec 2018 13:40:50 +0000 Subject: ecp5: Speed up timing analysis Signed-off-by: David Shah --- ecp5/arch.cc | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'ecp5/arch.cc') diff --git a/ecp5/arch.cc b/ecp5/arch.cc index 7de5c7aa..0d6b6a55 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -602,7 +602,7 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort // Data for -8 grade if (cell->type == id_TRELLIS_SLICE) { - bool has_carry = str_or_default(cell->params, id("MODE"), "LOGIC") == "CCU2"; + bool has_carry = cell->sliceInfo.is_carry; if (fromPort == id_A0 || fromPort == id_B0 || fromPort == id_C0 || fromPort == id_D0 || fromPort == id_A1 || fromPort == id_B1 || fromPort == id_C1 || fromPort == id_D1 || fromPort == id_M0 || fromPort == id_M1 || fromPort == id_FXA || fromPort == id_FXB || fromPort == id_FCI) { @@ -639,7 +639,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in auto disconnected = [cell](IdString p) { return !cell->ports.count(p) || cell->ports.at(p).net == nullptr; }; clockInfoCount = 0; if (cell->type == id_TRELLIS_SLICE) { - int sd0 = int_or_default(cell->params, id("REG0_SD"), 0), sd1 = int_or_default(cell->params, id("REG1_SD"), 0); + int sd0 = cell->sliceInfo.sd0, sd1 = cell->sliceInfo.sd1; if (port == id_CLK || port == id_WCK) return TMG_CLOCK_INPUT; if (port == id_A0 || port == id_A1 || port == id_B0 || port == id_B1 || port == id_C0 || port == id_C1 || @@ -782,8 +782,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port info.hold = getDelayFromNS(0); info.clockToQ = getDelayFromNS(0); if (cell->type == id_TRELLIS_SLICE) { - int sd0 = int_or_default(cell->params, id("REG0_SD"), 0), sd1 = int_or_default(cell->params, id("REG1_SD"), 0); - + int sd0 = cell->sliceInfo.sd0, sd1 = cell->sliceInfo.sd1; if (port == id_WD0 || port == id_WD1 || port == id_WAD0 || port == id_WAD1 || port == id_WAD2 || port == id_WAD3 || port == id_WRE) { info.edge = RISING_EDGE; -- cgit v1.2.3 From af3ff143be312b0f73289955bd513925f2bb7c4f Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 8 Jan 2019 10:52:03 +0000 Subject: ecp5: Improve delay model Signed-off-by: David Shah --- ecp5/arch.cc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'ecp5/arch.cc') diff --git a/ecp5/arch.cc b/ecp5/arch.cc index 0d6b6a55..1abb8af0 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -448,16 +448,17 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const auto src_loc = est_location(src), dst_loc = est_location(dst); - return (240 - 20 * args.speed) * (abs(src_loc.first - dst_loc.first) + abs(src_loc.second - dst_loc.second)); + return (110 - 10 * args.speed) + (200 - 20 * args.speed) * (abs(src_loc.first - dst_loc.first) + abs(src_loc.second - dst_loc.second)); } delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const { const auto &driver = net_info->driver; + if (driver.port == id_FCO && sink.port == id_FCI) + return 0; auto driver_loc = getBelLocation(driver.cell->bel); auto sink_loc = getBelLocation(sink.cell->bel); - - return (240 - 20 * args.speed) * (abs(driver_loc.x - sink_loc.x) + abs(driver_loc.y - sink_loc.y)); + return (110 - 10 * args.speed) + (200 - 20 * args.speed) * (abs(driver_loc.x - sink_loc.x) + abs(driver_loc.y - sink_loc.y)); } bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; } -- cgit v1.2.3 From f5b11ce075544d00ccafaf4363d099b6f1806335 Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 8 Jan 2019 13:06:02 +0000 Subject: ecp5: Implement budget overrides for carry chains and SLICE muxes Signed-off-by: David Shah --- ecp5/arch.cc | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'ecp5/arch.cc') diff --git a/ecp5/arch.cc b/ecp5/arch.cc index 1abb8af0..ad207d14 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -454,14 +454,24 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const { const auto &driver = net_info->driver; - if (driver.port == id_FCO && sink.port == id_FCI) + if ((driver.port == id_FCO && sink.port == id_FCI) || sink.port == id_FXA || sink.port == id_FXB) return 0; auto driver_loc = getBelLocation(driver.cell->bel); auto sink_loc = getBelLocation(sink.cell->bel); return (110 - 10 * args.speed) + (200 - 20 * args.speed) * (abs(driver_loc.x - sink_loc.x) + abs(driver_loc.y - sink_loc.y)); } -bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; } +bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { + if (net_info->driver.port == id_FCO && sink.port == id_FCI) { + return true; + budget = 0; + } else if (sink.port == id_FXA || sink.port == id_FXB) { + return true; + budget = 0; + } else { + return false; + } +} // ----------------------------------------------------------------------- -- cgit v1.2.3 From 55b0b60d9d58961bfefea66fcc197b399424d9d6 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 7 Feb 2019 19:19:15 +0000 Subject: ecp5: Router performance improvements Signed-off-by: David Shah --- ecp5/arch.cc | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) (limited to 'ecp5/arch.cc') diff --git a/ecp5/arch.cc b/ecp5/arch.cc index ad207d14..2bce0b01 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -427,6 +427,16 @@ BelId Arch::getBelByLocation(Loc loc) const delay_t Arch::estimateDelay(WireId src, WireId dst) const { + WireId cursor = dst; + + int num_uh = locInfo(dst)->wire_data[dst.index].num_uphill; + if (num_uh < 6) { + for (auto uh : getPipsUphill(dst)) { + if (getPipSrcWire(uh) == src) + return getPipDelay(uh).maxDelay(); + } + } + auto est_location = [&](WireId w) -> std::pair { if (w.location.x == 0 && w.location.y == 0) { // Global wires @@ -448,7 +458,8 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const auto src_loc = est_location(src), dst_loc = est_location(dst); - return (110 - 10 * args.speed) + (200 - 20 * args.speed) * (abs(src_loc.first - dst_loc.first) + abs(src_loc.second - dst_loc.second)); + int dx = abs(src_loc.first - dst_loc.first), dy = abs(src_loc.second - dst_loc.second); + return (130 - 13 * args.speed) * (4 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5))); } delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const @@ -458,16 +469,18 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const return 0; auto driver_loc = getBelLocation(driver.cell->bel); auto sink_loc = getBelLocation(sink.cell->bel); - return (110 - 10 * args.speed) + (200 - 20 * args.speed) * (abs(driver_loc.x - sink_loc.x) + abs(driver_loc.y - sink_loc.y)); + + int dx = abs(driver_loc.x - sink_loc.x), dy = abs(driver_loc.y - sink_loc.y); + return (130 - 13 * args.speed) * (4 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5))); } bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { if (net_info->driver.port == id_FCO && sink.port == id_FCI) { - return true; budget = 0; - } else if (sink.port == id_FXA || sink.port == id_FXB) { return true; + } else if (sink.port == id_FXA || sink.port == id_FXB) { budget = 0; + return true; } else { return false; } -- cgit v1.2.3 From 4ec2bd1e5deebf738e35ecf594a958cb0166f4af Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 25 Feb 2019 10:54:24 +0000 Subject: ecp5: Fix global clock routing with multiclock DPRAM Signed-off-by: David Shah --- ecp5/arch.cc | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'ecp5/arch.cc') diff --git a/ecp5/arch.cc b/ecp5/arch.cc index 2bce0b01..bec9278d 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -459,7 +459,8 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const auto src_loc = est_location(src), dst_loc = est_location(dst); int dx = abs(src_loc.first - dst_loc.first), dy = abs(src_loc.second - dst_loc.second); - return (130 - 13 * args.speed) * (4 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5))); + return (130 - 13 * args.speed) * + (4 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5))); } delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const @@ -471,10 +472,12 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const auto sink_loc = getBelLocation(sink.cell->bel); int dx = abs(driver_loc.x - sink_loc.x), dy = abs(driver_loc.y - sink_loc.y); - return (130 - 13 * args.speed) * (4 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5))); + return (130 - 13 * args.speed) * + (4 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5))); } -bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { +bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const +{ if (net_info->driver.port == id_FCO && sink.port == id_FCI) { budget = 0; return true; -- cgit v1.2.3 From f363dd2d3c8d00b4d237208d394ed185203a6890 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 25 Feb 2019 11:04:13 +0000 Subject: ecp5: Delay tuning Signed-off-by: David Shah --- ecp5/arch.cc | 49 +++++++++++++++++++++++++++++++------------------ 1 file changed, 31 insertions(+), 18 deletions(-) (limited to 'ecp5/arch.cc') diff --git a/ecp5/arch.cc b/ecp5/arch.cc index bec9278d..cc529df8 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -437,30 +437,27 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const } } - auto est_location = [&](WireId w) -> std::pair { - if (w.location.x == 0 && w.location.y == 0) { - // Global wires - const auto &wire = locInfo(w)->wire_data[w.index]; - // Use location of first downhill bel or pip, if available - if (wire.num_bel_pins > 0) { - return std::make_pair(wire.bel_pins[0].rel_bel_loc.x, wire.bel_pins[0].rel_bel_loc.y); - } else if (wire.num_downhill > 0) { - return std::make_pair(wire.pips_downhill[0].rel_loc.x, wire.pips_downhill[0].rel_loc.y); - } else if (wire.num_uphill > 0) { - return std::make_pair(wire.pips_uphill[0].rel_loc.x, wire.pips_uphill[0].rel_loc.y); - } else { - return std::make_pair(0, 0); - } + auto est_location = [&](WireId w) -> std::pair { + const auto &wire = locInfo(w)->wire_data[w.index]; + if (wire.num_bel_pins > 0) { + return std::make_pair(w.location.x + wire.bel_pins[0].rel_bel_loc.x, + w.location.y + wire.bel_pins[0].rel_bel_loc.y); + } else if (wire.num_downhill > 0) { + return std::make_pair(w.location.x + wire.pips_downhill[0].rel_loc.x, + w.location.y + wire.pips_downhill[0].rel_loc.y); + } else if (wire.num_uphill > 0) { + return std::make_pair(w.location.x + wire.pips_uphill[0].rel_loc.x, + w.location.y + wire.pips_uphill[0].rel_loc.y); } else { - return std::make_pair(w.location.x, w.location.y); + return std::make_pair(int(w.location.x), int(w.location.y)); } }; auto src_loc = est_location(src), dst_loc = est_location(dst); int dx = abs(src_loc.first - dst_loc.first), dy = abs(src_loc.second - dst_loc.second); - return (130 - 13 * args.speed) * - (4 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5))); + return (130 - 25 * args.speed) * + (8 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5))); } delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const @@ -471,8 +468,24 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const auto driver_loc = getBelLocation(driver.cell->bel); auto sink_loc = getBelLocation(sink.cell->bel); + // Encourage use of direct interconnect + if (driver_loc.x == sink_loc.x && driver_loc.y == sink_loc.y) { + if ((sink.port == id_A0 || sink.port == id_A1) && (driver.port == id_F1) && + (driver_loc.z == 2 || driver_loc.z == 3)) + return 0; + if ((sink.port == id_B0 || sink.port == id_B1) && (driver.port == id_F1) && + (driver_loc.z == 0 || driver_loc.z == 1)) + return 0; + if ((sink.port == id_C0 || sink.port == id_C1) && (driver.port == id_F0) && + (driver_loc.z == 2 || driver_loc.z == 3)) + return 0; + if ((sink.port == id_D0 || sink.port == id_D1) && (driver.port == id_F0) && + (driver_loc.z == 0 || driver_loc.z == 1)) + return 0; + } + int dx = abs(driver_loc.x - sink_loc.x), dy = abs(driver_loc.y - sink_loc.y); - return (130 - 13 * args.speed) * + return (130 - 25 * args.speed) * (4 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5))); } -- cgit v1.2.3 From a0fa16439942d15e9be745ec074fc1ba3a2a7c95 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 25 Feb 2019 11:06:33 +0000 Subject: ecp5: Add criticality-based LUT permutation Signed-off-by: David Shah --- ecp5/arch.cc | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'ecp5/arch.cc') diff --git a/ecp5/arch.cc b/ecp5/arch.cc index cc529df8..fdc9c8fc 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -486,7 +486,7 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const int dx = abs(driver_loc.x - sink_loc.x), dy = abs(driver_loc.y - sink_loc.y); return (130 - 25 * args.speed) * - (4 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5))); + (6 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5))); } bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const @@ -504,7 +504,17 @@ bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay // ----------------------------------------------------------------------- +<<<<<<< HEAD bool Arch::place() { return placer1(getCtx(), Placer1Cfg(getCtx())); } +======= +bool Arch::place() +{ + bool result = placer_heap(getCtx()); + if (result) + permute_luts(); + return result; +} +>>>>>>> 136e030... lut permutation bool Arch::route() { -- cgit v1.2.3 From 95a85c8ea76cdd0a1c5824200451569366c9eb8c Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 25 Feb 2019 11:07:21 +0000 Subject: ecp5: Improve packing density Signed-off-by: David Shah --- ecp5/arch.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'ecp5/arch.cc') diff --git a/ecp5/arch.cc b/ecp5/arch.cc index fdc9c8fc..cd5fa0cb 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -457,7 +457,7 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const int dx = abs(src_loc.first - dst_loc.first), dy = abs(src_loc.second - dst_loc.second); return (130 - 25 * args.speed) * - (8 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5))); + (6 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5))); } delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const -- cgit v1.2.3 From df79d94944b4d92207be7ddedc6424b7c931f313 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 25 Feb 2019 11:07:55 +0000 Subject: ecp5: DELAY fixes Signed-off-by: David Shah --- ecp5/arch.cc | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'ecp5/arch.cc') diff --git a/ecp5/arch.cc b/ecp5/arch.cc index cd5fa0cb..da0f7b1a 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -504,17 +504,13 @@ bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay // ----------------------------------------------------------------------- -<<<<<<< HEAD -bool Arch::place() { return placer1(getCtx(), Placer1Cfg(getCtx())); } -======= bool Arch::place() { - bool result = placer_heap(getCtx()); + bool result = placer1(getCtx(), Placer1Cfg(getCtx())); if (result) permute_luts(); return result; } ->>>>>>> 136e030... lut permutation bool Arch::route() { -- cgit v1.2.3