From ad18cdb08787c4ecc88edaec353a96f59135c62d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 18 Jun 2018 13:35:25 +0200
Subject: Rename Chip to Arch and ChipArgs to ArchArgs

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 common/design.h      | 4 ++--
 common/nextpnr.cc    | 2 +-
 common/place_sa.cc   | 8 ++++----
 common/pybindings.cc | 2 +-
 4 files changed, 8 insertions(+), 8 deletions(-)

(limited to 'common')

diff --git a/common/design.h b/common/design.h
index e763ed48..13c66d4e 100644
--- a/common/design.h
+++ b/common/design.h
@@ -72,9 +72,9 @@ struct CellInfo
 
 struct Design
 {
-    struct Chip chip;
+    struct Arch chip;
 
-    Design(ChipArgs args) : chip(args)
+    Design(ArchArgs args) : chip(args)
     {
         // ...
     }
diff --git a/common/nextpnr.cc b/common/nextpnr.cc
index d177fe71..374a5edb 100644
--- a/common/nextpnr.cc
+++ b/common/nextpnr.cc
@@ -35,7 +35,7 @@ void IdString::initialize()
 void IdString::initialize_add(const char *s, int idx)
 {
     assert(database_str_to_idx->count(s) == 0);
-    assert(database_idx_to_str->size() == idx);
+    assert(int(database_idx_to_str->size()) == idx);
     auto insert_rc = database_str_to_idx->insert({s, idx});
     database_idx_to_str->push_back(&insert_rc.first->first);
 }
diff --git a/common/place_sa.cc b/common/place_sa.cc
index 25297d31..f1c3dea2 100644
--- a/common/place_sa.cc
+++ b/common/place_sa.cc
@@ -78,7 +78,7 @@ static void place_initial(Design *design, CellInfo *cell, rnd_state &rnd)
         BelId best_bel = BelId();
         float best_score = std::numeric_limits<float>::infinity(),
               best_ripup_score = std::numeric_limits<float>::infinity();
-        Chip &chip = design->chip;
+        Arch &chip = design->chip;
         CellInfo *ripup_target = nullptr;
         BelId ripup_bel = BelId();
         if (cell->bel != BelId()) {
@@ -141,7 +141,7 @@ struct SAState
 };
 
 // Get the total estimated wirelength for a net
-static float get_wirelength(Chip *chip, NetInfo *net)
+static float get_wirelength(Arch *chip, NetInfo *net)
 {
     float wirelength = 0;
     int driver_x = 0, driver_y = 0;
@@ -181,7 +181,7 @@ static bool try_swap_position(Design *design, CellInfo *cell, BelId newBel,
     static std::vector<std::pair<NetInfo *, float>> new_lengths;
     new_lengths.clear();
     update.clear();
-    Chip &chip = design->chip;
+    Arch &chip = design->chip;
     BelId oldBel = cell->bel;
     IdString other = chip.getBelCell(newBel, true);
     CellInfo *other_cell = nullptr;
@@ -264,7 +264,7 @@ swap_fail:
 BelId random_bel_for_cell(Design *design, CellInfo *cell, SAState &state,
                           rnd_state &rnd)
 {
-    Chip &chip = design->chip;
+    Arch &chip = design->chip;
     BelType targetType = belTypeFromId(cell->type);
     int x = 0, y = 0;
     chip.estimatePosition(cell->bel, x, y);
diff --git a/common/pybindings.cc b/common/pybindings.cc
index 89f98716..3621d27a 100644
--- a/common/pybindings.cc
+++ b/common/pybindings.cc
@@ -57,7 +57,7 @@ void parse_json_shim(std::string filename, Design &d)
 }
 
 // Create a new Chip and load design from json file
-Design load_design_shim(std::string filename, ChipArgs args)
+Design load_design_shim(std::string filename, ArchArgs args)
 {
     Design d(args);
     parse_json_shim(filename, d);
-- 
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