From 9c52afcf5fabd888ec7d89e506ebe00c5a1a3640 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 16 Nov 2018 13:25:51 +0000 Subject: clangformat Signed-off-by: David Shah --- common/nextpnr.h | 5 +---- common/place_common.cc | 3 ++- common/router1.cc | 21 +++++++++++---------- common/timing.cc | 29 +++++++++++++++++++---------- 4 files changed, 33 insertions(+), 25 deletions(-) (limited to 'common') diff --git a/common/nextpnr.h b/common/nextpnr.h index a6617ae4..d58ae529 100644 --- a/common/nextpnr.h +++ b/common/nextpnr.h @@ -579,10 +579,7 @@ struct BaseCtx const Context *getCtx() const { return reinterpret_cast(this); } - const char *nameOf(IdString name) const - { - return name.c_str(this); - } + const char *nameOf(IdString name) const { return name.c_str(this); } template const char *nameOf(const T *obj) const { diff --git a/common/place_common.cc b/common/place_common.cc index a13a963c..b3eb4267 100644 --- a/common/place_common.cc +++ b/common/place_common.cc @@ -37,7 +37,8 @@ wirelen_t get_net_metric(const Context *ctx, const NetInfo *net, MetricType type if (driver_gb) return 0; int clock_count; - bool timing_driven = ctx->timing_driven && type == MetricType::COST && ctx->getPortTimingClass(driver_cell, net->driver.port, clock_count) != TMG_IGNORE; + bool timing_driven = ctx->timing_driven && type == MetricType::COST && + ctx->getPortTimingClass(driver_cell, net->driver.port, clock_count) != TMG_IGNORE; delay_t negative_slack = 0; delay_t worst_slack = std::numeric_limits::max(); Loc driver_loc = ctx->getBelLocation(driver_cell->bel); diff --git a/common/router1.cc b/common/router1.cc index 958c24d4..198461bc 100644 --- a/common/router1.cc +++ b/common/router1.cc @@ -34,7 +34,10 @@ struct arc_key int user_idx; bool operator==(const arc_key &other) const { return (net_info == other.net_info) && (user_idx == other.user_idx); } - bool operator<(const arc_key &other) const { return net_info == other.net_info ? user_idx < other.user_idx : net_info->name < other.net_info->name; } + bool operator<(const arc_key &other) const + { + return net_info == other.net_info ? user_idx < other.user_idx : net_info->name < other.net_info->name; + } struct Hash { @@ -375,21 +378,20 @@ struct Router1 if (dst_wire == WireId()) log_error("No wire found for port %s on destination cell %s.\n", - ctx->nameOf(net_info->users[user_idx].port), - ctx->nameOf(net_info->users[user_idx].cell)); + ctx->nameOf(net_info->users[user_idx].port), ctx->nameOf(net_info->users[user_idx].cell)); if (dst_to_arc.count(dst_wire)) { if (dst_to_arc.at(dst_wire).net_info == net_info) continue; - log_error("Found two arcs with same sink wire %s: %s (%d) vs %s (%d)\n", - ctx->nameOfWire(dst_wire), ctx->nameOf(net_info), user_idx, - ctx->nameOf(dst_to_arc.at(dst_wire).net_info), dst_to_arc.at(dst_wire).user_idx); + log_error("Found two arcs with same sink wire %s: %s (%d) vs %s (%d)\n", ctx->nameOfWire(dst_wire), + ctx->nameOf(net_info), user_idx, ctx->nameOf(dst_to_arc.at(dst_wire).net_info), + dst_to_arc.at(dst_wire).user_idx); } if (src_to_net.count(dst_wire)) log_error("Wire %s is used as source and sink in different nets: %s vs %s (%d)\n", - ctx->nameOfWire(dst_wire), ctx->nameOf(src_to_net.at(dst_wire)), - ctx->nameOf(net_info), user_idx); + ctx->nameOfWire(dst_wire), ctx->nameOf(src_to_net.at(dst_wire)), ctx->nameOf(net_info), + user_idx); arc_key arc; arc.net_info = net_info; @@ -950,8 +952,7 @@ bool Context::checkRoutedDesign() const for (WireId w : dangling_wires) { if (logged_wires.count(w) == 0) - log(" loop: %s -> %s\n", - ctx->nameOfWire(ctx->getPipSrcWire(net_info->wires.at(w).pip)), + log(" loop: %s -> %s\n", ctx->nameOfWire(ctx->getPipSrcWire(net_info->wires.at(w).pip)), ctx->nameOfWire(w)); } } diff --git a/common/timing.cc b/common/timing.cc index 40e4d344..80be554c 100644 --- a/common/timing.cc +++ b/common/timing.cc @@ -237,9 +237,11 @@ struct Timing } } if (ctx->force) - log_warning("timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc.\n"); + log_warning("timing analysis failed due to presence of combinatorial loops, incomplete specification " + "of timing ports, etc.\n"); else - log_error("timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc.\n"); + log_error("timing analysis failed due to presence of combinatorial loops, incomplete specification of " + "timing ports, etc.\n"); } // Go forwards topographically to find the maximum arrival time and max path length for each net @@ -639,7 +641,8 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p auto driver_wire = ctx->getNetinfoSourceWire(net); auto sink_wire = ctx->getNetinfoSinkWire(net, *sink); log_info(" prediction: %f ns estimate: %f ns\n", - ctx->getDelayNS(ctx->predictDelay(net, *sink)), ctx->getDelayNS(ctx->estimateDelay(driver_wire, sink_wire))); + ctx->getDelayNS(ctx->predictDelay(net, *sink)), + ctx->getDelayNS(ctx->estimateDelay(driver_wire, sink_wire))); auto cursor = sink_wire; delay_t delay; while (driver_wire != cursor) { @@ -648,7 +651,8 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p auto pip = it->second.pip; NPNR_ASSERT(pip != PipId()); delay = ctx->getPipDelay(pip).maxDelay(); - log_info(" %1.3f %s\n", ctx->getDelayNS(delay), ctx->getPipName(pip).c_str(ctx)); + log_info(" %1.3f %s\n", ctx->getDelayNS(delay), + ctx->getPipName(pip).c_str(ctx)); cursor = ctx->getPipSrcWire(pip); } } @@ -658,9 +662,12 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p for (auto &clock : clock_reports) { log_break(); - std::string start = clock.second.first.start.edge == FALLING_EDGE ? std::string("negedge") : std::string("posedge"); - std::string end = clock.second.first.end.edge == FALLING_EDGE ? std::string("negedge") : std::string("posedge"); - log_info("Critical path report for clock '%s' (%s -> %s):\n", clock.first.c_str(ctx), start.c_str(), end.c_str()); + std::string start = + clock.second.first.start.edge == FALLING_EDGE ? std::string("negedge") : std::string("posedge"); + std::string end = + clock.second.first.end.edge == FALLING_EDGE ? std::string("negedge") : std::string("posedge"); + log_info("Critical path report for clock '%s' (%s -> %s):\n", clock.first.c_str(ctx), start.c_str(), + end.c_str()); auto &crit_path = clock.second.second.ports; print_path_report(clock.second.first, crit_path); } @@ -684,10 +691,12 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p const int width = max_width - clock_name.size(); if (ctx->nets.at(clock.first)->clkconstr) { float target = 1000 / ctx->getDelayNS(ctx->nets.at(clock.first)->clkconstr->period.minDelay()); - log_info("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "", clock_name.c_str(), - clock_fmax[clock.first], (target < clock_fmax[clock.first]) ? "PASS" : "FAIL", target); + log_info("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "", + clock_name.c_str(), clock_fmax[clock.first], + (target < clock_fmax[clock.first]) ? "PASS" : "FAIL", target); } else { - log_info("Max frequency for clock %*s'%s': %.02f MHz\n", width, "", clock_name.c_str(), clock_fmax[clock.first]); + log_info("Max frequency for clock %*s'%s': %.02f MHz\n", width, "", clock_name.c_str(), + clock_fmax[clock.first]); } } for (auto &eclock : empty_clocks) { -- cgit v1.2.3