From 5e48758b30caf8ecc91c3c416326a093b47a2e2d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 May 2018 10:47:35 +0200 Subject: Directory structure Signed-off-by: Clifford Wolf --- common/design.h | 95 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) create mode 100644 common/design.h (limited to 'common') diff --git a/common/design.h b/common/design.h new file mode 100644 index 00000000..421937eb --- /dev/null +++ b/common/design.h @@ -0,0 +1,95 @@ +/* + * nextpnr -- Next Generation PnR + * + * Copyright (C) 2018 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef DESIGN_H +#define DESIGN_H + +#include +#include +#include +#include +#include + +// replace with proper IdString later +typedef std::string IdString; + +// replace with haslib later +template using pool = std::unordered_set; +template using dict = std::unordered_map; +using std::vector; + +#include "chip.h" + +struct CellInfo; + +struct PortRef +{ + CellInfo *cell; + IdString port; +}; + +struct NetInfo +{ + IdString name; + PortRef driver; + vector users; + dict attrs; + + // wire -> (uphill_wire, delay) + dict> wires; +}; + +enum PortType +{ + PORT_IN = 0, + PORT_OUT = 1, + PORT_INOUT = 2 +}; + +struct PortInfo +{ + IdString name; + NetInfo *net; + PortType type; +}; + +struct CellInfo +{ + IdString name, type; + dict ports; + dict attrs, params; + + BelId bel; + // cell_port -> bel_pin + dict pins; +}; + +struct Design +{ + struct Chip chip; + + Design(ChipArgs args) : chip(args) { + // ... + } + + dict nets; + dict cells; +}; + +#endif -- cgit v1.2.3