From 23f2fff1c83eed5b80421c485cf887cf2d232f73 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 22 Mar 2019 10:39:05 +0000 Subject: clangformat Signed-off-by: David Shah --- common/placer1.cc | 2 +- common/timing.cc | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) (limited to 'common') diff --git a/common/placer1.cc b/common/placer1.cc index 9ebf3ee6..0c918f33 100644 --- a/common/placer1.cc +++ b/common/placer1.cc @@ -318,7 +318,7 @@ class SAPlacer "%.0f, wirelen = %.0f, dia = %d, Ra = %.02f \n", iter, temp, double(curr_timing_cost), double(curr_wirelen_cost), diameter, Raccept); - if (curr_wirelen_cost < 0.95 * avg_wirelen && curr_wirelen_cost > 0) { + if (curr_wirelen_cost < 0.95 * avg_wirelen && curr_wirelen_cost > 0) { avg_wirelen = 0.8 * avg_wirelen + 0.2 * curr_wirelen_cost; } else { double diam_next = diameter * (1.0 - 0.44 + Raccept); diff --git a/common/timing.cc b/common/timing.cc index 2a0af874..2ce9eea3 100644 --- a/common/timing.cc +++ b/common/timing.cc @@ -904,10 +904,9 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p if (!warn_on_failure || passed) log_info("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "", clock_name.c_str(), clock_fmax[clock.first], passed ? "PASS" : "FAIL", target); - else - if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false)) + else if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false)) log_warning("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "", - clock_name.c_str(), clock_fmax[clock.first], passed ? "PASS" : "FAIL", target); + clock_name.c_str(), clock_fmax[clock.first], passed ? "PASS" : "FAIL", target); else log_nonfatal_error("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "", clock_name.c_str(), clock_fmax[clock.first], passed ? "PASS" : "FAIL", target); -- cgit v1.2.3