From 91023d2a0e6c4d15b640f9c913565b8298f0a19c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 8 Aug 2018 08:31:08 -0700 Subject: Leave comment behind about removing false paths --- common/timing.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'common/timing.cc') diff --git a/common/timing.cc b/common/timing.cc index a3b5235a..c1be083d 100644 --- a/common/timing.cc +++ b/common/timing.cc @@ -92,7 +92,7 @@ struct Timing topographical_order.emplace_back(o->net); net_data.emplace(o->net, TimingData{clkToQ.maxDelay()}); } else { - // TODO: how to process ignore here + // TODO(eddieh): Generated clocks and ignored ports are currently added into the ordering as if it was a regular timing start point in order to enable the full topographical order to be computed, however these false nets (and their downstream paths) should not be in the final ordering if (portClass == TMG_STARTPOINT || portClass == TMG_GEN_CLOCK || portClass == TMG_IGNORE) { topographical_order.emplace_back(o->net); net_data.emplace(o->net, TimingData{}); -- cgit v1.2.3