From c0f1af87f6c1c6843e536a87ef88e39fa3428c5b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 17 Jul 2018 17:03:44 +0200 Subject: Add Loc struct for x/y/z bel locations Signed-off-by: Clifford Wolf --- common/nextpnr.h | 9 +++++++++ ice40/arch.h | 31 +++++++++++++++++++++++++++++-- 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/common/nextpnr.h b/common/nextpnr.h index 50465869..375e1cd7 100644 --- a/common/nextpnr.h +++ b/common/nextpnr.h @@ -157,6 +157,11 @@ struct GraphicElement std::string text; }; +struct Loc +{ + int x = -1, y = -1, z = -1; +}; + NEXTPNR_NAMESPACE_END #include "archdefs.h" @@ -310,6 +315,10 @@ struct Context : Arch Context(ArchArgs args) : Arch(args) {} + BelId getBelByLocation(Loc loc) const { + return getBelByLocation(loc.x, loc.y, loc.z); + } + // -------------------------------------------------------------- // provided by router1.cc diff --git a/ice40/arch.h b/ice40/arch.h index 5dab414b..d840c6ea 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -424,7 +424,34 @@ struct Arch : BaseCtx return range; } - BelRange getBelsAtSameTile(BelId bel) const; + Loc getBelLocation(BelId bel) const + { + Loc loc; + loc.x = chip_info->bel_data[bel.index].x; + loc.y = chip_info->bel_data[bel.index].y; + loc.z = chip_info->bel_data[bel.index].z; + return loc; + } + + BelId getBelByLocation(int x, int y, int z) const + { + // FIXME + return BelId(); + } + + BelRange getBelsByTile(int x, int y) const + { + BelRange range; + // FIXME + return range; + } + + bool getBelGlobalBuf(BelId bel) const + { + return chip_info->bel_data[bel.index].type == TYPE_SB_GB; + } + + BelRange getBelsAtSameTile(BelId bel) const NPNR_DEPRECATED; BelType getBelType(BelId bel) const { @@ -655,7 +682,7 @@ struct Arch : BaseCtx // ------------------------------------------------- - void estimatePosition(BelId bel, int &x, int &y, bool &gb) const; + void estimatePosition(BelId bel, int &x, int &y, bool &gb) const NPNR_DEPRECATED; delay_t estimateDelay(WireId src, WireId dst) const; delay_t getDelayEpsilon() const { return 20; } delay_t getRipupDelayPenalty() const { return 200; } -- cgit v1.2.3 From 3bad9c26cff1ba2da7f1810e5915246874780744 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 20 Jul 2018 11:36:32 +0200 Subject: ice40: Optimise reset/enable net checking Signed-off-by: David Shah --- ice40/arch.cc | 10 +++++++++- ice40/arch_place.cc | 14 ++++---------- ice40/archdefs.h | 1 + 3 files changed, 14 insertions(+), 11 deletions(-) diff --git a/ice40/arch.cc b/ice40/arch.cc index 1aa02294..786d8ba1 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -25,7 +25,7 @@ #include "placer1.h" #include "router1.h" #include "util.h" - +#include "cells.h" NEXTPNR_NAMESPACE_BEGIN // ----------------------------------------------------------------------- @@ -704,6 +704,14 @@ void Arch::assignArchInfo() NetInfo *ni = net.second.get(); if (isGlobalNet(ni)) ni->is_global = true; + ni->is_enable = false; + ni->is_reset = false; + for (auto usr : ni->users) { + if (is_enable_port(this, usr)) + ni->is_enable = true; + if (is_reset_port(this, usr)) + ni->is_reset = true; + } } for (auto &cell : getCtx()->cells) { CellInfo *ci = cell.second.get(); diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc index 1f2943a0..116ab7d3 100644 --- a/ice40/arch_place.cc +++ b/ice40/arch_place.cc @@ -108,21 +108,15 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const } else if (cell->type == id_sb_io) { return getBelPackagePin(bel) != ""; } else if (cell->type == id_sb_gb) { - bool is_reset = false, is_cen = false; NPNR_ASSERT(cell->ports.at(id_glb_buf_out).net != nullptr); - for (auto user : cell->ports.at(id_glb_buf_out).net->users) { - if (is_reset_port(this, user)) - is_reset = true; - if (is_enable_port(this, user)) - is_cen = true; - } + const NetInfo *net = cell->ports.at(id_glb_buf_out).net; IdString glb_net = getWireName(getWireBelPin(bel, PIN_GLOBAL_BUFFER_OUTPUT)); int glb_id = std::stoi(std::string("") + glb_net.str(this).back()); - if (is_reset && is_cen) + if (net->is_reset && net->is_enable) return false; - else if (is_reset) + else if (net->is_reset) return (glb_id % 2) == 0; - else if (is_cen) + else if (net->is_enable) return (glb_id % 2) == 1; else return true; diff --git a/ice40/archdefs.h b/ice40/archdefs.h index 55e2c2fb..14b0d2be 100644 --- a/ice40/archdefs.h +++ b/ice40/archdefs.h @@ -153,6 +153,7 @@ struct DecalId struct ArchNetInfo { bool is_global = false; + bool is_reset = false, is_enable = false; }; struct NetInfo; -- cgit v1.2.3 From 53034959f338c952f4cf905890e44aad2ba202ae Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 20 Jul 2018 13:27:21 +0200 Subject: Start adding bitstream reading for ice40 --- gui/designwidget.cc | 11 +--- ice40/bitstream.cc | 166 +++++++++++++++++++++++++++++++++++++++++----------- ice40/bitstream.h | 1 + ice40/main.cc | 8 +++ 4 files changed, 143 insertions(+), 43 deletions(-) diff --git a/gui/designwidget.cc b/gui/designwidget.cc index 4123bf30..d28b843b 100644 --- a/gui/designwidget.cc +++ b/gui/designwidget.cc @@ -334,16 +334,7 @@ void DesignWidget::newContext(Context *ctx) for (auto pip : nameToItem[2].toStdMap()) { pip_root->addChild(pip.second); } - - // Add nets to tree - nets_root = new QTreeWidgetItem(treeWidget); - nets_root->setText(0, "Nets"); - treeWidget->insertTopLevelItem(0, nets_root); - - // Add cells to tree - cells_root = new QTreeWidgetItem(treeWidget); - cells_root->setText(0, "Cells"); - treeWidget->insertTopLevelItem(0, cells_root); + updateTree(); } void DesignWidget::updateTree() diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index c12fa90e..b0f6260d 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -157,6 +157,42 @@ void configure_extra_cell(chipconfig_t &config, const Context *ctx, CellInfo *ce } } +std::string tagTileType(TileType &tile) +{ + if (tile == TILE_NONE) + return ""; + switch (tile) { + case TILE_LOGIC: + return ".logic_tile"; + break; + case TILE_IO: + return ".io_tile"; + break; + case TILE_RAMB: + return ".ramb_tile"; + break; + case TILE_RAMT: + return ".ramt_tile"; + break; + case TILE_DSP0: + return ".dsp0_tile"; + break; + case TILE_DSP1: + return ".dsp1_tile"; + break; + case TILE_DSP2: + return ".dsp2_tile"; + break; + case TILE_DSP3: + return ".dsp3_tile"; + break; + case TILE_IPCON: + return ".ipcon_tile"; + break; + default: + NPNR_ASSERT(false); + } +} void write_asc(const Context *ctx, std::ostream &out) { // [y][x][row][col] @@ -443,39 +479,7 @@ void write_asc(const Context *ctx, std::ostream &out) for (int y = 0; y < ci.height; y++) { for (int x = 0; x < ci.width; x++) { TileType tile = tile_at(ctx, x, y); - if (tile == TILE_NONE) - continue; - switch (tile) { - case TILE_LOGIC: - out << ".logic_tile"; - break; - case TILE_IO: - out << ".io_tile"; - break; - case TILE_RAMB: - out << ".ramb_tile"; - break; - case TILE_RAMT: - out << ".ramt_tile"; - break; - case TILE_DSP0: - out << ".dsp0_tile"; - break; - case TILE_DSP1: - out << ".dsp1_tile"; - break; - case TILE_DSP2: - out << ".dsp2_tile"; - break; - case TILE_DSP3: - out << ".dsp3_tile"; - break; - case TILE_IPCON: - out << ".ipcon_tile"; - break; - default: - NPNR_ASSERT(false); - } + out << tagTileType(tile); out << " " << x << " " << y << std::endl; for (auto row : config.at(y).at(x)) { for (auto col : row) { @@ -526,4 +530,100 @@ void write_asc(const Context *ctx, std::ostream &out) } } +void read_config(Context *ctx, std::istream &in, chipconfig_t &config) +{ + constexpr size_t line_buf_size = 65536; + char buffer[line_buf_size]; + int tile_x = -1, tile_y = -1, line_nr = -1; + + while (1) { + in.getline(buffer, line_buf_size); + if (buffer[0] == '.') { + line_nr = -1; + const char *tok = strtok(buffer, " \t\r\n"); + + if (!strcmp(tok, ".device")) { + std::string config_device = strtok(nullptr, " \t\r\n"); + std::string expected; + switch (ctx->args.type) { + case ArchArgs::LP384: + expected = "384"; + break; + case ArchArgs::HX1K: + case ArchArgs::LP1K: + expected = "1k"; + break; + case ArchArgs::HX8K: + case ArchArgs::LP8K: + expected = "8k"; + break; + case ArchArgs::UP5K: + expected = "5k"; + break; + default: + log_error("unsupported device type"); + } + if (expected != config_device) + log_error("device type does not match"); + } else if (!strcmp(tok, ".io_tile") || !strcmp(tok, ".logic_tile") || !strcmp(tok, ".ramb_tile") || + !strcmp(tok, ".ramt_tile") || !strcmp(tok, ".ipcon_tile") || !strcmp(tok, ".dsp0_tile") || + !strcmp(tok, ".dsp1_tile") || !strcmp(tok, ".dsp2_tile") || !strcmp(tok, ".dsp3_tile")) { + line_nr = 0; + tile_x = atoi(strtok(nullptr, " \t\r\n")); + tile_y = atoi(strtok(nullptr, " \t\r\n")); + + TileType tile = tile_at(ctx, tile_x, tile_y); + if (tok != tagTileType(tile)) + log_error("Wrong tile type for specified position"); + + } else if (!strcmp(tok, ".extra_bit")) { + /* + int b = atoi(strtok(nullptr, " \t\r\n")); + int x = atoi(strtok(nullptr, " \t\r\n")); + int y = atoi(strtok(nullptr, " \t\r\n")); + std::tuple key(b, x, y); + extra_bits.insert(key); + */ + } else if (!strcmp(tok, ".sym")) { + int net = atoi(strtok(nullptr, " \t\r\n")); (void)net; + const char *name = strtok(nullptr, " \t\r\n"); + std::unique_ptr created_net = std::unique_ptr(new NetInfo); + created_net->name = ctx->id(name); + ctx->nets[created_net->name] = std::move(created_net); + } + } else if (line_nr >= 0 && strlen(buffer) > 0) { + if (line_nr > int(config.at(tile_y).at(tile_x).size() - 1)) + log_error("Invalid data in input asc file"); + for (int i = 0; buffer[i] == '0' || buffer[i] == '1'; i++) + config.at(tile_y).at(tile_x).at(line_nr).at(i) = (buffer[i] == '1') ? 1 : 0; + line_nr++; + } + if (in.eof()) + break; + } +} + +bool read_asc(Context *ctx, std::istream &in) +{ + try { + // [y][x][row][col] + const ChipInfoPOD &ci = *ctx->chip_info; + const BitstreamInfoPOD &bi = *ci.bits_info; + chipconfig_t config; + config.resize(ci.height); + for (int y = 0; y < ci.height; y++) { + config.at(y).resize(ci.width); + for (int x = 0; x < ci.width; x++) { + TileType tile = tile_at(ctx, x, y); + int rows = bi.tiles_nonrouting[tile].rows; + int cols = bi.tiles_nonrouting[tile].cols; + config.at(y).at(x).resize(rows, std::vector(cols)); + } + } + read_config(ctx, in, config); + return true; + } catch (log_execution_error_exception) { + return false; + } +} NEXTPNR_NAMESPACE_END diff --git a/ice40/bitstream.h b/ice40/bitstream.h index 2b6cda1d..41a2ae68 100644 --- a/ice40/bitstream.h +++ b/ice40/bitstream.h @@ -27,6 +27,7 @@ NEXTPNR_NAMESPACE_BEGIN void write_asc(const Context *ctx, std::ostream &out); +bool read_asc(Context *ctx, std::istream &in); NEXTPNR_NAMESPACE_END diff --git a/ice40/main.cc b/ice40/main.cc index e77bdd34..c14b6086 100644 --- a/ice40/main.cc +++ b/ice40/main.cc @@ -95,6 +95,7 @@ int main(int argc, char *argv[]) options.add_options()("json", po::value(), "JSON design file to ingest"); options.add_options()("pcf", po::value(), "PCF constraints file to ingest"); options.add_options()("asc", po::value(), "asc bitstream file to write"); + options.add_options()("read", po::value(), "asc bitstream file to read"); options.add_options()("seed", po::value(), "seed value for random number generator"); options.add_options()("version,V", "show version"); options.add_options()("tmfuzz", "run path delay estimate fuzzer"); @@ -353,6 +354,13 @@ int main(int argc, char *argv[]) if (vm.count("no-tmdriv")) ctx->timing_driven = false; + if (vm.count("read")) { + std::string filename = vm["read"].as(); + std::ifstream f(filename); + if (!read_asc(ctx.get(), f)) + log_error("Loading ASC failed.\n"); + } + #ifndef NO_GUI if (vm.count("gui")) { Application a(argc, argv); -- cgit v1.2.3 From 6c835d76f27af79813299419780c039eb2a8b02e Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 20 Jul 2018 14:06:53 +0200 Subject: Few more checks on parameters and error eol --- ice40/bitstream.cc | 8 ++++---- ice40/main.cc | 16 +++++++++++++--- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index b0f6260d..1b6a9425 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -227,7 +227,7 @@ void write_asc(const Context *ctx, std::ostream &out) out << ".device 5k" << std::endl; break; default: - NPNR_ASSERT_FALSE("unsupported device type"); + NPNR_ASSERT_FALSE("unsupported device type\n"); } // Set pips for (auto pip : ctx->getPips()) { @@ -561,10 +561,10 @@ void read_config(Context *ctx, std::istream &in, chipconfig_t &config) expected = "5k"; break; default: - log_error("unsupported device type"); + log_error("unsupported device type\n"); } if (expected != config_device) - log_error("device type does not match"); + log_error("device type does not match\n"); } else if (!strcmp(tok, ".io_tile") || !strcmp(tok, ".logic_tile") || !strcmp(tok, ".ramb_tile") || !strcmp(tok, ".ramt_tile") || !strcmp(tok, ".ipcon_tile") || !strcmp(tok, ".dsp0_tile") || !strcmp(tok, ".dsp1_tile") || !strcmp(tok, ".dsp2_tile") || !strcmp(tok, ".dsp3_tile")) { @@ -574,7 +574,7 @@ void read_config(Context *ctx, std::istream &in, chipconfig_t &config) TileType tile = tile_at(ctx, tile_x, tile_y); if (tok != tagTileType(tile)) - log_error("Wrong tile type for specified position"); + log_error("Wrong tile type for specified position\n"); } else if (!strcmp(tok, ".extra_bit")) { /* diff --git a/ice40/main.cc b/ice40/main.cc index c14b6086..652196a1 100644 --- a/ice40/main.cc +++ b/ice40/main.cc @@ -66,6 +66,12 @@ void svg_dump_decal(const Context *ctx, const DecalXY &decal) } } +void conflicting_options(const boost::program_options::variables_map &vm, const char *opt1, const char *opt2) +{ + if (vm.count(opt1) && !vm[opt1].defaulted() && vm.count(opt2) && !vm[opt2].defaulted()) + log_error((std::string("Conflicting options '") + opt1 + "' and '" + opt2 + "'.").c_str()); +} + int main(int argc, char *argv[]) { try { @@ -122,13 +128,17 @@ int main(int argc, char *argv[]) po::store(parsed, vm); po::notify(vm); - } - - catch (std::exception &e) { + } catch (std::exception &e) { std::cout << e.what() << "\n"; return 1; } + conflicting_options(vm, "read", "json"); +#ifndef ICE40_HX1K_ONLY + if ((vm.count("lp384") + vm.count("lp1k") + vm.count("lp8k") + vm.count("hx1k") + vm.count("hx8k") + + vm.count("up5k")) > 1) + log_error("Only one device type can be set\n"); +#endif if (vm.count("help") || argc == 1) { help: std::cout << boost::filesystem::basename(argv[0]) -- cgit v1.2.3 From f6fa0300ae95a0896a12b9acf0c7e76851c13d37 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 20 Jul 2018 17:33:57 +0200 Subject: Improve iCE40 and common Loc code Signed-off-by: Clifford Wolf --- common/nextpnr.h | 19 +++++++++++++++++++ ice40/arch.cc | 31 ++++++++++++++++++++++++++++++- ice40/arch.h | 15 +++------------ ice40/archdefs.h | 2 -- 4 files changed, 52 insertions(+), 15 deletions(-) diff --git a/common/nextpnr.h b/common/nextpnr.h index 8ef958cd..4cdc4d00 100644 --- a/common/nextpnr.h +++ b/common/nextpnr.h @@ -27,6 +27,8 @@ #include #include +#include + #ifndef NEXTPNR_H #define NEXTPNR_H @@ -161,10 +163,27 @@ struct GraphicElement struct Loc { int x = -1, y = -1, z = -1; + + bool operator==(const Loc &other) const { return (x == other.x) && (y == other.y) && (z == other.z); } + bool operator!=(const Loc &other) const { return (x != other.x) || (y != other.y) || (z == other.z); } }; NEXTPNR_NAMESPACE_END +namespace std { +template <> struct hash +{ + std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX Loc &obj) const noexcept + { + std::size_t seed = 0; + boost::hash_combine(seed, hash()(obj.x)); + boost::hash_combine(seed, hash()(obj.y)); + boost::hash_combine(seed, hash()(obj.z)); + return seed; + } +}; +} // namespace std + #include "archdefs.h" NEXTPNR_NAMESPACE_BEGIN diff --git a/ice40/arch.cc b/ice40/arch.cc index 786d8ba1..ceafca17 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -255,11 +255,40 @@ BelId Arch::getBelByName(IdString name) const return ret; } +BelId Arch::getBelByLocation(int x, int y, int z) const +{ + if (bel_by_loc.empty()) { + for (int i = 0; i < chip_info->num_bels; i++) + bel_by_loc[getBelLocation(BelId{i})] = i; + } + + auto it = bel_by_loc.find(Loc{x, y, z}); + if (it != bel_by_loc.end()) + return BelId{it->second}; + return BelId(); +} + +BelRange Arch::getBelsByTile(int x, int y) const +{ + // In iCE40 chipdb bels at the same tile are consecutive and dense z ordinates are used + BelRange br; + br.b.cursor = Arch::getBelByLocation(x, y, 0); + br.e.cursor = br.b.cursor; + + if (br.e.cursor != -1) { + while (br.e.cursor < chip_info->num_bels && + chip_info->bel_data[br.e.cursor].x == x && + chip_info->bel_data[br.e.cursor].y == y) + br.e.cursor++; + } + + return br; +} + BelRange Arch::getBelsAtSameTile(BelId bel) const { BelRange br; NPNR_ASSERT(bel != BelId()); - // This requires Bels at the same tile are consecutive int x = chip_info->bel_data[bel.index].x; int y = chip_info->bel_data[bel.index].y; int start = bel.index, end = bel.index; diff --git a/ice40/arch.h b/ice40/arch.h index 805876e4..f86428a9 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -350,6 +350,7 @@ struct Arch : BaseCtx mutable std::unordered_map bel_by_name; mutable std::unordered_map wire_by_name; mutable std::unordered_map pip_by_name; + mutable std::unordered_map bel_by_loc; std::vector bel_to_cell; std::vector wire_to_net; @@ -449,18 +450,8 @@ struct Arch : BaseCtx return loc; } - BelId getBelByLocation(int x, int y, int z) const - { - // FIXME - return BelId(); - } - - BelRange getBelsByTile(int x, int y) const - { - BelRange range; - // FIXME - return range; - } + BelId getBelByLocation(int x, int y, int z) const; + BelRange getBelsByTile(int x, int y) const; bool getBelGlobalBuf(BelId bel) const { diff --git a/ice40/archdefs.h b/ice40/archdefs.h index 14b0d2be..dec6f702 100644 --- a/ice40/archdefs.h +++ b/ice40/archdefs.h @@ -21,8 +21,6 @@ #error Include "archdefs.h" via "nextpnr.h" only. #endif -#include - NEXTPNR_NAMESPACE_BEGIN typedef int delay_t; -- cgit v1.2.3 From fd8239e170a7391d9c25d8681083507d9960abef Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 20 Jul 2018 18:09:22 +0200 Subject: Add Location APIs to generic arch Signed-off-by: Clifford Wolf --- common/nextpnr.h | 4 ---- generic/arch.cc | 28 +++++++++++++++++++--------- generic/arch.h | 13 ++++++++++--- ice40/arch.cc | 26 +++++++++++++++++++------- ice40/arch.h | 2 +- 5 files changed, 49 insertions(+), 24 deletions(-) diff --git a/common/nextpnr.h b/common/nextpnr.h index 4cdc4d00..40fd3d13 100644 --- a/common/nextpnr.h +++ b/common/nextpnr.h @@ -339,10 +339,6 @@ struct Context : Arch Context(ArchArgs args) : Arch(args) {} - BelId getBelByLocation(Loc loc) const { - return getBelByLocation(loc.x, loc.y, loc.z); - } - // -------------------------------------------------------------- // provided by router1.cc diff --git a/generic/arch.cc b/generic/arch.cc index 390830aa..b7ec847e 100644 --- a/generic/arch.cc +++ b/generic/arch.cc @@ -29,8 +29,8 @@ void Arch::addWire(IdString name, int x, int y) NPNR_ASSERT(wires.count(name) == 0); WireInfo &wi = wires[name]; wi.name = name; - wi.grid_x = x; - wi.grid_y = y; + wi.x = x; + wi.y = y; wire_ids.push_back(name); } @@ -62,18 +62,28 @@ void Arch::addAlias(IdString name, IdString srcWire, IdString dstWire, DelayInfo pip_ids.push_back(name); } -void Arch::addBel(IdString name, IdString type, int x, int y, bool gb) +void Arch::addBel(IdString name, IdString type, int x, int y, int z, bool gb) { + Loc loc; + loc.x = x; + loc.y = y; + loc.z = z; + NPNR_ASSERT(bels.count(name) == 0); + NPNR_ASSERT(bel_by_loc.count(loc) == 0); BelInfo &bi = bels[name]; bi.name = name; bi.type = type; - bi.grid_x = x; - bi.grid_y = y; + bi.x = x; + bi.y = y; + bi.z = z; bi.gb = gb; bel_ids.push_back(name); bel_ids_by_type[type].push_back(name); + + bel_by_loc[loc] = name; + bels_by_tile[x][y].push_back(name); } void Arch::addBelInput(IdString bel, IdString name, IdString wire) @@ -348,8 +358,8 @@ const std::vector &Arch::getGroupGroups(GroupId group) const { return g void Arch::estimatePosition(BelId bel, int &x, int &y, bool &gb) const { - x = bels.at(bel).grid_x; - y = bels.at(bel).grid_y; + x = bels.at(bel).x; + y = bels.at(bel).y; gb = bels.at(bel).gb; } @@ -357,8 +367,8 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const { const WireInfo &s = wires.at(src); const WireInfo &d = wires.at(dst); - int dx = abs(s.grid_x - d.grid_x); - int dy = abs(s.grid_y - d.grid_y); + int dx = abs(s.x - d.x); + int dy = abs(s.y - d.y); return (dx + dy) * grid_distance_to_delay; } diff --git a/generic/arch.h b/generic/arch.h index 5d7ac540..ea4bb565 100644 --- a/generic/arch.h +++ b/generic/arch.h @@ -44,7 +44,7 @@ struct WireInfo BelPin uphill_bel_pin; std::vector downhill_bel_pins; DecalXY decalxy; - int grid_x, grid_y; + int x, y; }; struct PinInfo @@ -59,7 +59,7 @@ struct BelInfo IdString name, type, bound_cell; std::unordered_map pins; DecalXY decalxy; - int grid_x, grid_y; + int x, y, z; bool gb; }; @@ -85,6 +85,9 @@ struct Arch : BaseCtx std::vector bel_ids, wire_ids, pip_ids; std::unordered_map> bel_ids_by_type; + std::unordered_map bel_by_loc; + std::unordered_map>> bels_by_tile; + std::unordered_map> decal_graphics; DecalXY frame_decalxy; @@ -94,7 +97,7 @@ struct Arch : BaseCtx void addPip(IdString name, IdString srcWire, IdString dstWire, DelayInfo delay); void addAlias(IdString name, IdString srcWire, IdString dstWire, DelayInfo delay); - void addBel(IdString name, IdString type, int x, int y, bool gb); + void addBel(IdString name, IdString type, int x, int y, int z, bool gb); void addBelInput(IdString bel, IdString name, IdString wire); void addBelOutput(IdString bel, IdString name, IdString wire); void addBelInout(IdString bel, IdString name, IdString wire); @@ -129,6 +132,10 @@ struct Arch : BaseCtx BelId getBelByName(IdString name) const; IdString getBelName(BelId bel) const; + Loc getBelLocation(BelId bel) const; + BelId getBelByLocation(Loc loc) const; + std::vector getBelsByTile(int x, int y) const; + bool getBelGlobalBuf(BelId bel) const; uint32_t getBelChecksum(BelId bel) const; void bindBel(BelId bel, IdString cell, PlaceStrength strength); void unbindBel(BelId bel); diff --git a/ice40/arch.cc b/ice40/arch.cc index ceafca17..e9a7d2b6 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -255,24 +255,36 @@ BelId Arch::getBelByName(IdString name) const return ret; } -BelId Arch::getBelByLocation(int x, int y, int z) const +BelId Arch::getBelByLocation(Loc loc) const { + BelId bel; + if (bel_by_loc.empty()) { - for (int i = 0; i < chip_info->num_bels; i++) - bel_by_loc[getBelLocation(BelId{i})] = i; + for (int i = 0; i < chip_info->num_bels; i++) { + BelId b; + b.index = i; + bel_by_loc[getBelLocation(b)] = i; + } } - auto it = bel_by_loc.find(Loc{x, y, z}); + auto it = bel_by_loc.find(loc); if (it != bel_by_loc.end()) - return BelId{it->second}; - return BelId(); + bel.index = it->second; + + return bel; } BelRange Arch::getBelsByTile(int x, int y) const { // In iCE40 chipdb bels at the same tile are consecutive and dense z ordinates are used BelRange br; - br.b.cursor = Arch::getBelByLocation(x, y, 0); + + Loc loc; + loc.x = x; + loc.y = y; + loc.z = 0; + + br.b.cursor = Arch::getBelByLocation(loc).index; br.e.cursor = br.b.cursor; if (br.e.cursor != -1) { diff --git a/ice40/arch.h b/ice40/arch.h index f86428a9..beba2ccf 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -450,7 +450,7 @@ struct Arch : BaseCtx return loc; } - BelId getBelByLocation(int x, int y, int z) const; + BelId getBelByLocation(Loc loc) const; BelRange getBelsByTile(int x, int y) const; bool getBelGlobalBuf(BelId bel) const -- cgit v1.2.3 From 34ec70e88bb48e71fbc7eaf3b9c9e1c643ed6adb Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 20 Jul 2018 18:42:05 +0200 Subject: Bind wires to net --- ice40/bitstream.cc | 1266 ++++++++++++++++++++++++++-------------------------- 1 file changed, 637 insertions(+), 629 deletions(-) diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 1b6a9425..1acaad0e 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -1,629 +1,637 @@ -/* - * nextpnr -- Next Generation Place and Route - * - * Copyright (C) 2018 Clifford Wolf - * Copyright (C) 2018 David Shah - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ -#include "bitstream.h" -#include -#include -#include "log.h" - -NEXTPNR_NAMESPACE_BEGIN - -inline TileType tile_at(const Context *ctx, int x, int y) -{ - return ctx->chip_info->tile_grid[y * ctx->chip_info->width + x]; -} - -const ConfigEntryPOD &find_config(const TileInfoPOD &tile, const std::string &name) -{ - for (int i = 0; i < tile.num_config_entries; i++) { - if (std::string(tile.entries[i].name.get()) == name) { - return tile.entries[i]; - } - } - NPNR_ASSERT_FALSE_STR("unable to find config bit " + name); -} - -std::tuple get_ieren(const BitstreamInfoPOD &bi, int8_t x, int8_t y, int8_t z) -{ - for (int i = 0; i < bi.num_ierens; i++) { - auto ie = bi.ierens[i]; - if (ie.iox == x && ie.ioy == y && ie.ioz == z) { - return std::make_tuple(ie.ierx, ie.iery, ie.ierz); - } - } - // No pin at this location - return std::make_tuple(-1, -1, -1); -}; - -void set_config(const TileInfoPOD &ti, std::vector> &tile_cfg, const std::string &name, bool value, - int index = -1) -{ - const ConfigEntryPOD &cfg = find_config(ti, name); - if (index == -1) { - for (int i = 0; i < cfg.num_bits; i++) { - int8_t &cbit = tile_cfg.at(cfg.bits[i].row).at(cfg.bits[i].col); - if (cbit && !value) - log_error("clearing already set config bit %s", name.c_str()); - cbit = value; - } - } else { - int8_t &cbit = tile_cfg.at(cfg.bits[index].row).at(cfg.bits[index].col); - cbit = value; - if (cbit && !value) - log_error("clearing already set config bit %s[%d]", name.c_str(), index); - } -} - -int get_param_or_def(const CellInfo *cell, const IdString param, int defval = 0) -{ - auto found = cell->params.find(param); - if (found != cell->params.end()) - return std::stoi(found->second); - else - return defval; -} - -std::string get_param_str_or_def(const CellInfo *cell, const IdString param, std::string defval = "") -{ - auto found = cell->params.find(param); - if (found != cell->params.end()) - return found->second; - else - return defval; -} - -char get_hexdigit(int i) { return std::string("0123456789ABCDEF").at(i); } - -static const BelConfigPOD &get_ec_config(const ChipInfoPOD *chip, BelId bel) -{ - for (int i = 0; i < chip->num_belcfgs; i++) { - if (chip->bel_config[i].bel_index == bel.index) - return chip->bel_config[i]; - } - NPNR_ASSERT_FALSE("failed to find bel config"); -} - -typedef std::vector>>> chipconfig_t; - -static void set_ec_cbit(chipconfig_t &config, const Context *ctx, const BelConfigPOD &cell_cbits, std::string name, - bool value) -{ - const ChipInfoPOD *chip = ctx->chip_info; - - for (int i = 0; i < cell_cbits.num_entries; i++) { - const auto &cbit = cell_cbits.entries[i]; - if (cbit.entry_name.get() == name) { - const auto &ti = chip->bits_info->tiles_nonrouting[tile_at(ctx, cbit.x, cbit.y)]; - set_config(ti, config.at(cbit.y).at(cbit.x), std::string("IpConfig.") + cbit.cbit_name.get(), value); - return; - } - } - NPNR_ASSERT_FALSE_STR("failed to config extra cell config bit " + name); -} - -void configure_extra_cell(chipconfig_t &config, const Context *ctx, CellInfo *cell, - const std::vector> ¶ms, bool string_style) -{ - const ChipInfoPOD *chip = ctx->chip_info; - const auto &bc = get_ec_config(chip, cell->bel); - for (auto p : params) { - std::vector value; - if (string_style) { - // Lattice's weird string style params, not sure if - // prefixes other than 0b should be supported, only 0b features in docs - std::string raw = get_param_str_or_def(cell, ctx->id(p.first), "0b0"); - assert(raw.substr(0, 2) == "0b"); - raw = raw.substr(2); - value.resize(raw.length()); - for (int i = 0; i < (int)raw.length(); i++) { - if (raw[i] == '1') { - value[(raw.length() - 1) - i] = 1; - } else { - assert(raw[i] == '0'); - value[(raw.length() - 1) - i] = 0; - } - } - } else { - int ival = get_param_or_def(cell, ctx->id(p.first), 0); - - for (int i = 0; i < p.second; i++) - value.push_back((ival >> i) & 0x1); - } - - value.resize(p.second); - if (p.second == 1) { - set_ec_cbit(config, ctx, bc, p.first, value.at(0)); - } else { - for (int i = 0; i < p.second; i++) { - set_ec_cbit(config, ctx, bc, p.first + "_" + std::to_string(i), value.at(i)); - } - } - } -} - -std::string tagTileType(TileType &tile) -{ - if (tile == TILE_NONE) - return ""; - switch (tile) { - case TILE_LOGIC: - return ".logic_tile"; - break; - case TILE_IO: - return ".io_tile"; - break; - case TILE_RAMB: - return ".ramb_tile"; - break; - case TILE_RAMT: - return ".ramt_tile"; - break; - case TILE_DSP0: - return ".dsp0_tile"; - break; - case TILE_DSP1: - return ".dsp1_tile"; - break; - case TILE_DSP2: - return ".dsp2_tile"; - break; - case TILE_DSP3: - return ".dsp3_tile"; - break; - case TILE_IPCON: - return ".ipcon_tile"; - break; - default: - NPNR_ASSERT(false); - } -} -void write_asc(const Context *ctx, std::ostream &out) -{ - // [y][x][row][col] - const ChipInfoPOD &ci = *ctx->chip_info; - const BitstreamInfoPOD &bi = *ci.bits_info; - chipconfig_t config; - config.resize(ci.height); - for (int y = 0; y < ci.height; y++) { - config.at(y).resize(ci.width); - for (int x = 0; x < ci.width; x++) { - TileType tile = tile_at(ctx, x, y); - int rows = bi.tiles_nonrouting[tile].rows; - int cols = bi.tiles_nonrouting[tile].cols; - config.at(y).at(x).resize(rows, std::vector(cols)); - } - } - out << ".comment from next-pnr" << std::endl; - - switch (ctx->args.type) { - case ArchArgs::LP384: - out << ".device 384" << std::endl; - break; - case ArchArgs::HX1K: - case ArchArgs::LP1K: - out << ".device 1k" << std::endl; - break; - case ArchArgs::HX8K: - case ArchArgs::LP8K: - out << ".device 8k" << std::endl; - break; - case ArchArgs::UP5K: - out << ".device 5k" << std::endl; - break; - default: - NPNR_ASSERT_FALSE("unsupported device type\n"); - } - // Set pips - for (auto pip : ctx->getPips()) { - if (ctx->pip_to_net[pip.index] != IdString()) { - const PipInfoPOD &pi = ci.pip_data[pip.index]; - const SwitchInfoPOD &swi = bi.switches[pi.switch_index]; - for (int i = 0; i < swi.num_bits; i++) { - bool val = (pi.switch_mask & (1 << ((swi.num_bits - 1) - i))) != 0; - int8_t &cbit = config.at(swi.y).at(swi.x).at(swi.cbits[i].row).at(swi.cbits[i].col); - if (bool(cbit) != 0) - NPNR_ASSERT(false); - cbit = val; - } - } - } - // Set logic cell config - for (auto &cell : ctx->cells) { - BelId bel = cell.second.get()->bel; - if (bel == BelId()) { - std::cout << "Found unplaced cell " << cell.first.str(ctx) << " while generating bitstream!" << std::endl; - continue; - } - const BelInfoPOD &beli = ci.bel_data[bel.index]; - int x = beli.x, y = beli.y, z = beli.z; - if (cell.second->type == ctx->id("ICESTORM_LC")) { - const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_LOGIC]; - unsigned lut_init = get_param_or_def(cell.second.get(), ctx->id("LUT_INIT")); - bool neg_clk = get_param_or_def(cell.second.get(), ctx->id("NEG_CLK")); - bool dff_enable = get_param_or_def(cell.second.get(), ctx->id("DFF_ENABLE")); - bool async_sr = get_param_or_def(cell.second.get(), ctx->id("ASYNC_SR")); - bool set_noreset = get_param_or_def(cell.second.get(), ctx->id("SET_NORESET")); - bool carry_enable = get_param_or_def(cell.second.get(), ctx->id("CARRY_ENABLE")); - std::vector lc(20, false); - // From arachne-pnr - static std::vector lut_perm = { - 4, 14, 15, 5, 6, 16, 17, 7, 3, 13, 12, 2, 1, 11, 10, 0, - }; - for (int i = 0; i < 16; i++) { - if ((lut_init >> i) & 0x1) - lc.at(lut_perm.at(i)) = true; - } - lc.at(8) = carry_enable; - lc.at(9) = dff_enable; - lc.at(18) = set_noreset; - lc.at(19) = async_sr; - - for (int i = 0; i < 20; i++) - set_config(ti, config.at(y).at(x), "LC_" + std::to_string(z), lc.at(i), i); - if (dff_enable) - set_config(ti, config.at(y).at(x), "NegClk", neg_clk); - - bool carry_const = get_param_or_def(cell.second.get(), ctx->id("CIN_CONST")); - bool carry_set = get_param_or_def(cell.second.get(), ctx->id("CIN_SET")); - if (carry_const) { - if (!ctx->force) - NPNR_ASSERT(z == 0); - set_config(ti, config.at(y).at(x), "CarryInSet", carry_set); - } - } else if (cell.second->type == ctx->id("SB_IO")) { - const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO]; - unsigned pin_type = get_param_or_def(cell.second.get(), ctx->id("PIN_TYPE")); - bool neg_trigger = get_param_or_def(cell.second.get(), ctx->id("NEG_TRIGGER")); - bool pullup = get_param_or_def(cell.second.get(), ctx->id("PULLUP")); - for (int i = 0; i < 6; i++) { - bool val = (pin_type >> i) & 0x01; - set_config(ti, config.at(y).at(x), "IOB_" + std::to_string(z) + ".PINTYPE_" + std::to_string(i), val); - } - set_config(ti, config.at(y).at(x), "NegClk", neg_trigger); - auto ieren = get_ieren(bi, x, y, z); - int iex, iey, iez; - std::tie(iex, iey, iez) = ieren; - NPNR_ASSERT(iez != -1); - - bool input_en = false; - if ((ctx->wire_to_net[ctx->getWireBelPin(bel, PIN_D_IN_0).index] != IdString()) || - (ctx->wire_to_net[ctx->getWireBelPin(bel, PIN_D_IN_1).index] != IdString())) { - input_en = true; - } - - if (ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K) { - set_config(ti, config.at(iey).at(iex), "IoCtrl.IE_" + std::to_string(iez), !input_en); - set_config(ti, config.at(iey).at(iex), "IoCtrl.REN_" + std::to_string(iez), !pullup); - } else { - set_config(ti, config.at(iey).at(iex), "IoCtrl.IE_" + std::to_string(iez), input_en); - set_config(ti, config.at(iey).at(iex), "IoCtrl.REN_" + std::to_string(iez), !pullup); - } - - if (ctx->args.type == ArchArgs::UP5K) { - if (iez == 0) { - set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_39", !pullup); - } else if (iez == 1) { - set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_35", !pullup); - } - } - } else if (cell.second->type == ctx->id("SB_GB")) { - // no cell config bits - } else if (cell.second->type == ctx->id("ICESTORM_RAM")) { - const BelInfoPOD &beli = ci.bel_data[bel.index]; - int x = beli.x, y = beli.y; - const TileInfoPOD &ti_ramt = bi.tiles_nonrouting[TILE_RAMT]; - const TileInfoPOD &ti_ramb = bi.tiles_nonrouting[TILE_RAMB]; - if (!(ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K)) { - set_config(ti_ramb, config.at(y).at(x), "RamConfig.PowerUp", true); - } - bool negclk_r = get_param_or_def(cell.second.get(), ctx->id("NEG_CLK_R")); - bool negclk_w = get_param_or_def(cell.second.get(), ctx->id("NEG_CLK_W")); - int write_mode = get_param_or_def(cell.second.get(), ctx->id("WRITE_MODE")); - int read_mode = get_param_or_def(cell.second.get(), ctx->id("READ_MODE")); - set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w); - set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r); - - set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_0", write_mode & 0x1); - set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_1", write_mode & 0x2); - set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_2", read_mode & 0x1); - set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_3", read_mode & 0x2); - } else if (cell.second->type == ctx->id("SB_WARMBOOT") || cell.second->type == ctx->id("ICESTORM_LFOSC")) { - // No config needed - } else if (cell.second->type == ctx->id("ICESTORM_SPRAM")) { - const BelInfoPOD &beli = ci.bel_data[bel.index]; - int x = beli.x, y = beli.y, z = beli.z; - NPNR_ASSERT(ctx->args.type == ArchArgs::UP5K); - if (x == 0 && y == 0) { - const TileInfoPOD &ti_ipcon = bi.tiles_nonrouting[TILE_IPCON]; - if (z == 1) { - set_config(ti_ipcon, config.at(1).at(0), "IpConfig.CBIT_0", true); - } else if (z == 2) { - set_config(ti_ipcon, config.at(1).at(0), "IpConfig.CBIT_1", true); - } else { - NPNR_ASSERT(false); - } - } else if (x == 25 && y == 0) { - const TileInfoPOD &ti_ipcon = bi.tiles_nonrouting[TILE_IPCON]; - if (z == 3) { - set_config(ti_ipcon, config.at(1).at(25), "IpConfig.CBIT_0", true); - } else if (z == 4) { - set_config(ti_ipcon, config.at(1).at(25), "IpConfig.CBIT_1", true); - } else { - NPNR_ASSERT(false); - } - } - } else if (cell.second->type == ctx->id("ICESTORM_DSP")) { - const std::vector> mac16_params = {{"C_REG", 1}, - {"A_REG", 1}, - {"B_REG", 1}, - {"D_REG", 1}, - {"TOP_8x8_MULT_REG", 1}, - {"BOT_8x8_MULT_REG", 1}, - {"PIPELINE_16x16_MULT_REG1", 1}, - {"PIPELINE_16x16_MULT_REG2", 1}, - {"TOPOUTPUT_SELECT", 2}, - {"TOPADDSUB_LOWERINPUT", 2}, - {"TOPADDSUB_UPPERINPUT", 1}, - {"TOPADDSUB_CARRYSELECT", 2}, - {"BOTOUTPUT_SELECT", 2}, - {"BOTADDSUB_LOWERINPUT", 2}, - {"BOTADDSUB_UPPERINPUT", 1}, - {"BOTADDSUB_CARRYSELECT", 2}, - {"MODE_8x8", 1}, - {"A_SIGNED", 1}, - {"B_SIGNED", 1}}; - configure_extra_cell(config, ctx, cell.second.get(), mac16_params, false); - } else { - NPNR_ASSERT(false); - } - } - // Set config bits in unused IO and RAM - for (auto bel : ctx->getBels()) { - if (ctx->bel_to_cell[bel.index] == IdString() && ctx->getBelType(bel) == TYPE_SB_IO) { - const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO]; - const BelInfoPOD &beli = ci.bel_data[bel.index]; - int x = beli.x, y = beli.y, z = beli.z; - auto ieren = get_ieren(bi, x, y, z); - int iex, iey, iez; - std::tie(iex, iey, iez) = ieren; - if (iez != -1) { - if (ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K) { - set_config(ti, config.at(iey).at(iex), "IoCtrl.IE_" + std::to_string(iez), true); - set_config(ti, config.at(iey).at(iex), "IoCtrl.REN_" + std::to_string(iez), false); - } - } - } else if (ctx->bel_to_cell[bel.index] == IdString() && ctx->getBelType(bel) == TYPE_ICESTORM_RAM) { - const BelInfoPOD &beli = ci.bel_data[bel.index]; - int x = beli.x, y = beli.y; - const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_RAMB]; - if ((ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K)) { - set_config(ti, config.at(y).at(x), "RamConfig.PowerUp", true); - } - } - } - - // Set other config bits - for (int y = 0; y < ci.height; y++) { - for (int x = 0; x < ci.width; x++) { - TileType tile = tile_at(ctx, x, y); - const TileInfoPOD &ti = bi.tiles_nonrouting[tile]; - - // set all ColBufCtrl bits (FIXME) - bool setColBufCtrl = true; - if (ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K) { - if (tile == TILE_RAMB || tile == TILE_RAMT) { - setColBufCtrl = (y == 3 || y == 5 || y == 11 || y == 13); - } else { - setColBufCtrl = (y == 4 || y == 5 || y == 12 || y == 13); - } - } else if (ctx->args.type == ArchArgs::LP8K || ctx->args.type == ArchArgs::HX8K) { - setColBufCtrl = (y == 8 || y == 9 || y == 24 || y == 25); - } else if (ctx->args.type == ArchArgs::UP5K) { - setColBufCtrl = (y == 4 || y == 5 || y == 14 || y == 15 || y == 26 || y == 27); - } - if (setColBufCtrl) { - set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_0", true); - set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_1", true); - set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_2", true); - set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_3", true); - set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_4", true); - set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_5", true); - set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_6", true); - set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_7", true); - } - - // Weird UltraPlus bits - if (tile == TILE_DSP0 || tile == TILE_DSP1 || tile == TILE_DSP2 || tile == TILE_DSP3 || - tile == TILE_IPCON) { - if (ctx->args.type == ArchArgs::UP5K && x == 25 && y == 14) { - // Mystery bits not set in this one tile - } else { - for (int lc_idx = 0; lc_idx < 8; lc_idx++) { - static const std::vector ip_dsp_lut_perm = { - 4, 14, 15, 5, 6, 16, 17, 7, 3, 13, 12, 2, 1, 11, 10, 0, - }; - for (int i = 0; i < 16; i++) - set_config(ti, config.at(y).at(x), "LC_" + std::to_string(lc_idx), ((i % 8) >= 4), - ip_dsp_lut_perm.at(i)); - if (tile == TILE_IPCON) - set_config(ti, config.at(y).at(x), - "Cascade.IPCON_LC0" + std::to_string(lc_idx) + "_inmux02_5", true); - else - set_config(ti, config.at(y).at(x), - "Cascade.MULT" + std::to_string(int(tile - TILE_DSP0)) + "_LC0" + - std::to_string(lc_idx) + "_inmux02_5", - true); - } - } - } - } - } - - // Write config out - for (int y = 0; y < ci.height; y++) { - for (int x = 0; x < ci.width; x++) { - TileType tile = tile_at(ctx, x, y); - out << tagTileType(tile); - out << " " << x << " " << y << std::endl; - for (auto row : config.at(y).at(x)) { - for (auto col : row) { - if (col == 1) - out << "1"; - else - out << "0"; - } - out << std::endl; - } - out << std::endl; - } - } - - // Write RAM init data - for (auto &cell : ctx->cells) { - if (cell.second->bel != BelId()) { - if (cell.second->type == ctx->id("ICESTORM_RAM")) { - const BelInfoPOD &beli = ci.bel_data[cell.second->bel.index]; - int x = beli.x, y = beli.y; - out << ".ram_data " << x << " " << y << std::endl; - for (int w = 0; w < 16; w++) { - std::vector bits(256); - std::string init = - get_param_str_or_def(cell.second.get(), ctx->id(std::string("INIT_") + get_hexdigit(w))); - NPNR_ASSERT(init != ""); - for (size_t i = 0; i < init.size(); i++) { - bool val = (init.at((init.size() - 1) - i) == '1'); - bits.at(i) = val; - } - for (int i = bits.size() - 4; i >= 0; i -= 4) { - int c = bits.at(i) + (bits.at(i + 1) << 1) + (bits.at(i + 2) << 2) + (bits.at(i + 3) << 3); - out << char(std::tolower(get_hexdigit(c))); - } - out << std::endl; - } - out << std::endl; - } - } - } - - // Write symbols - // const bool write_symbols = 1; - for (auto wire : ctx->getWires()) { - IdString net = ctx->getBoundWireNet(wire); - if (net != IdString()) - out << ".sym " << wire.index << " " << net.str(ctx) << std::endl; - } -} - -void read_config(Context *ctx, std::istream &in, chipconfig_t &config) -{ - constexpr size_t line_buf_size = 65536; - char buffer[line_buf_size]; - int tile_x = -1, tile_y = -1, line_nr = -1; - - while (1) { - in.getline(buffer, line_buf_size); - if (buffer[0] == '.') { - line_nr = -1; - const char *tok = strtok(buffer, " \t\r\n"); - - if (!strcmp(tok, ".device")) { - std::string config_device = strtok(nullptr, " \t\r\n"); - std::string expected; - switch (ctx->args.type) { - case ArchArgs::LP384: - expected = "384"; - break; - case ArchArgs::HX1K: - case ArchArgs::LP1K: - expected = "1k"; - break; - case ArchArgs::HX8K: - case ArchArgs::LP8K: - expected = "8k"; - break; - case ArchArgs::UP5K: - expected = "5k"; - break; - default: - log_error("unsupported device type\n"); - } - if (expected != config_device) - log_error("device type does not match\n"); - } else if (!strcmp(tok, ".io_tile") || !strcmp(tok, ".logic_tile") || !strcmp(tok, ".ramb_tile") || - !strcmp(tok, ".ramt_tile") || !strcmp(tok, ".ipcon_tile") || !strcmp(tok, ".dsp0_tile") || - !strcmp(tok, ".dsp1_tile") || !strcmp(tok, ".dsp2_tile") || !strcmp(tok, ".dsp3_tile")) { - line_nr = 0; - tile_x = atoi(strtok(nullptr, " \t\r\n")); - tile_y = atoi(strtok(nullptr, " \t\r\n")); - - TileType tile = tile_at(ctx, tile_x, tile_y); - if (tok != tagTileType(tile)) - log_error("Wrong tile type for specified position\n"); - - } else if (!strcmp(tok, ".extra_bit")) { - /* - int b = atoi(strtok(nullptr, " \t\r\n")); - int x = atoi(strtok(nullptr, " \t\r\n")); - int y = atoi(strtok(nullptr, " \t\r\n")); - std::tuple key(b, x, y); - extra_bits.insert(key); - */ - } else if (!strcmp(tok, ".sym")) { - int net = atoi(strtok(nullptr, " \t\r\n")); (void)net; - const char *name = strtok(nullptr, " \t\r\n"); - std::unique_ptr created_net = std::unique_ptr(new NetInfo); - created_net->name = ctx->id(name); - ctx->nets[created_net->name] = std::move(created_net); - } - } else if (line_nr >= 0 && strlen(buffer) > 0) { - if (line_nr > int(config.at(tile_y).at(tile_x).size() - 1)) - log_error("Invalid data in input asc file"); - for (int i = 0; buffer[i] == '0' || buffer[i] == '1'; i++) - config.at(tile_y).at(tile_x).at(line_nr).at(i) = (buffer[i] == '1') ? 1 : 0; - line_nr++; - } - if (in.eof()) - break; - } -} - -bool read_asc(Context *ctx, std::istream &in) -{ - try { - // [y][x][row][col] - const ChipInfoPOD &ci = *ctx->chip_info; - const BitstreamInfoPOD &bi = *ci.bits_info; - chipconfig_t config; - config.resize(ci.height); - for (int y = 0; y < ci.height; y++) { - config.at(y).resize(ci.width); - for (int x = 0; x < ci.width; x++) { - TileType tile = tile_at(ctx, x, y); - int rows = bi.tiles_nonrouting[tile].rows; - int cols = bi.tiles_nonrouting[tile].cols; - config.at(y).at(x).resize(rows, std::vector(cols)); - } - } - read_config(ctx, in, config); - return true; - } catch (log_execution_error_exception) { - return false; - } -} -NEXTPNR_NAMESPACE_END +/* + * nextpnr -- Next Generation Place and Route + * + * Copyright (C) 2018 Clifford Wolf + * Copyright (C) 2018 David Shah + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +#include "bitstream.h" +#include +#include +#include "log.h" + +NEXTPNR_NAMESPACE_BEGIN + +inline TileType tile_at(const Context *ctx, int x, int y) +{ + return ctx->chip_info->tile_grid[y * ctx->chip_info->width + x]; +} + +const ConfigEntryPOD &find_config(const TileInfoPOD &tile, const std::string &name) +{ + for (int i = 0; i < tile.num_config_entries; i++) { + if (std::string(tile.entries[i].name.get()) == name) { + return tile.entries[i]; + } + } + NPNR_ASSERT_FALSE_STR("unable to find config bit " + name); +} + +std::tuple get_ieren(const BitstreamInfoPOD &bi, int8_t x, int8_t y, int8_t z) +{ + for (int i = 0; i < bi.num_ierens; i++) { + auto ie = bi.ierens[i]; + if (ie.iox == x && ie.ioy == y && ie.ioz == z) { + return std::make_tuple(ie.ierx, ie.iery, ie.ierz); + } + } + // No pin at this location + return std::make_tuple(-1, -1, -1); +}; + +void set_config(const TileInfoPOD &ti, std::vector> &tile_cfg, const std::string &name, bool value, + int index = -1) +{ + const ConfigEntryPOD &cfg = find_config(ti, name); + if (index == -1) { + for (int i = 0; i < cfg.num_bits; i++) { + int8_t &cbit = tile_cfg.at(cfg.bits[i].row).at(cfg.bits[i].col); + if (cbit && !value) + log_error("clearing already set config bit %s", name.c_str()); + cbit = value; + } + } else { + int8_t &cbit = tile_cfg.at(cfg.bits[index].row).at(cfg.bits[index].col); + cbit = value; + if (cbit && !value) + log_error("clearing already set config bit %s[%d]", name.c_str(), index); + } +} + +int get_param_or_def(const CellInfo *cell, const IdString param, int defval = 0) +{ + auto found = cell->params.find(param); + if (found != cell->params.end()) + return std::stoi(found->second); + else + return defval; +} + +std::string get_param_str_or_def(const CellInfo *cell, const IdString param, std::string defval = "") +{ + auto found = cell->params.find(param); + if (found != cell->params.end()) + return found->second; + else + return defval; +} + +char get_hexdigit(int i) { return std::string("0123456789ABCDEF").at(i); } + +static const BelConfigPOD &get_ec_config(const ChipInfoPOD *chip, BelId bel) +{ + for (int i = 0; i < chip->num_belcfgs; i++) { + if (chip->bel_config[i].bel_index == bel.index) + return chip->bel_config[i]; + } + NPNR_ASSERT_FALSE("failed to find bel config"); +} + +typedef std::vector>>> chipconfig_t; + +static void set_ec_cbit(chipconfig_t &config, const Context *ctx, const BelConfigPOD &cell_cbits, std::string name, + bool value) +{ + const ChipInfoPOD *chip = ctx->chip_info; + + for (int i = 0; i < cell_cbits.num_entries; i++) { + const auto &cbit = cell_cbits.entries[i]; + if (cbit.entry_name.get() == name) { + const auto &ti = chip->bits_info->tiles_nonrouting[tile_at(ctx, cbit.x, cbit.y)]; + set_config(ti, config.at(cbit.y).at(cbit.x), std::string("IpConfig.") + cbit.cbit_name.get(), value); + return; + } + } + NPNR_ASSERT_FALSE_STR("failed to config extra cell config bit " + name); +} + +void configure_extra_cell(chipconfig_t &config, const Context *ctx, CellInfo *cell, + const std::vector> ¶ms, bool string_style) +{ + const ChipInfoPOD *chip = ctx->chip_info; + const auto &bc = get_ec_config(chip, cell->bel); + for (auto p : params) { + std::vector value; + if (string_style) { + // Lattice's weird string style params, not sure if + // prefixes other than 0b should be supported, only 0b features in docs + std::string raw = get_param_str_or_def(cell, ctx->id(p.first), "0b0"); + assert(raw.substr(0, 2) == "0b"); + raw = raw.substr(2); + value.resize(raw.length()); + for (int i = 0; i < (int)raw.length(); i++) { + if (raw[i] == '1') { + value[(raw.length() - 1) - i] = 1; + } else { + assert(raw[i] == '0'); + value[(raw.length() - 1) - i] = 0; + } + } + } else { + int ival = get_param_or_def(cell, ctx->id(p.first), 0); + + for (int i = 0; i < p.second; i++) + value.push_back((ival >> i) & 0x1); + } + + value.resize(p.second); + if (p.second == 1) { + set_ec_cbit(config, ctx, bc, p.first, value.at(0)); + } else { + for (int i = 0; i < p.second; i++) { + set_ec_cbit(config, ctx, bc, p.first + "_" + std::to_string(i), value.at(i)); + } + } + } +} + +std::string tagTileType(TileType &tile) +{ + if (tile == TILE_NONE) + return ""; + switch (tile) { + case TILE_LOGIC: + return ".logic_tile"; + break; + case TILE_IO: + return ".io_tile"; + break; + case TILE_RAMB: + return ".ramb_tile"; + break; + case TILE_RAMT: + return ".ramt_tile"; + break; + case TILE_DSP0: + return ".dsp0_tile"; + break; + case TILE_DSP1: + return ".dsp1_tile"; + break; + case TILE_DSP2: + return ".dsp2_tile"; + break; + case TILE_DSP3: + return ".dsp3_tile"; + break; + case TILE_IPCON: + return ".ipcon_tile"; + break; + default: + NPNR_ASSERT(false); + } +} +void write_asc(const Context *ctx, std::ostream &out) +{ + // [y][x][row][col] + const ChipInfoPOD &ci = *ctx->chip_info; + const BitstreamInfoPOD &bi = *ci.bits_info; + chipconfig_t config; + config.resize(ci.height); + for (int y = 0; y < ci.height; y++) { + config.at(y).resize(ci.width); + for (int x = 0; x < ci.width; x++) { + TileType tile = tile_at(ctx, x, y); + int rows = bi.tiles_nonrouting[tile].rows; + int cols = bi.tiles_nonrouting[tile].cols; + config.at(y).at(x).resize(rows, std::vector(cols)); + } + } + out << ".comment from next-pnr" << std::endl; + + switch (ctx->args.type) { + case ArchArgs::LP384: + out << ".device 384" << std::endl; + break; + case ArchArgs::HX1K: + case ArchArgs::LP1K: + out << ".device 1k" << std::endl; + break; + case ArchArgs::HX8K: + case ArchArgs::LP8K: + out << ".device 8k" << std::endl; + break; + case ArchArgs::UP5K: + out << ".device 5k" << std::endl; + break; + default: + NPNR_ASSERT_FALSE("unsupported device type\n"); + } + // Set pips + for (auto pip : ctx->getPips()) { + if (ctx->pip_to_net[pip.index] != IdString()) { + const PipInfoPOD &pi = ci.pip_data[pip.index]; + const SwitchInfoPOD &swi = bi.switches[pi.switch_index]; + for (int i = 0; i < swi.num_bits; i++) { + bool val = (pi.switch_mask & (1 << ((swi.num_bits - 1) - i))) != 0; + int8_t &cbit = config.at(swi.y).at(swi.x).at(swi.cbits[i].row).at(swi.cbits[i].col); + if (bool(cbit) != 0) + NPNR_ASSERT(false); + cbit = val; + } + } + } + // Set logic cell config + for (auto &cell : ctx->cells) { + BelId bel = cell.second.get()->bel; + if (bel == BelId()) { + std::cout << "Found unplaced cell " << cell.first.str(ctx) << " while generating bitstream!" << std::endl; + continue; + } + if (cell.second->type == ctx->id("ICESTORM_LC")) { + const BelInfoPOD &beli = ci.bel_data[bel.index]; + int x = beli.x, y = beli.y, z = beli.z; + const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_LOGIC]; + unsigned lut_init = get_param_or_def(cell.second.get(), ctx->id("LUT_INIT")); + bool neg_clk = get_param_or_def(cell.second.get(), ctx->id("NEG_CLK")); + bool dff_enable = get_param_or_def(cell.second.get(), ctx->id("DFF_ENABLE")); + bool async_sr = get_param_or_def(cell.second.get(), ctx->id("ASYNC_SR")); + bool set_noreset = get_param_or_def(cell.second.get(), ctx->id("SET_NORESET")); + bool carry_enable = get_param_or_def(cell.second.get(), ctx->id("CARRY_ENABLE")); + std::vector lc(20, false); + // From arachne-pnr + static std::vector lut_perm = { + 4, 14, 15, 5, 6, 16, 17, 7, 3, 13, 12, 2, 1, 11, 10, 0, + }; + for (int i = 0; i < 16; i++) { + if ((lut_init >> i) & 0x1) + lc.at(lut_perm.at(i)) = true; + } + lc.at(8) = carry_enable; + lc.at(9) = dff_enable; + lc.at(18) = set_noreset; + lc.at(19) = async_sr; + + for (int i = 0; i < 20; i++) + set_config(ti, config.at(y).at(x), "LC_" + std::to_string(z), lc.at(i), i); + if (dff_enable) + set_config(ti, config.at(y).at(x), "NegClk", neg_clk); + + bool carry_const = get_param_or_def(cell.second.get(), ctx->id("CIN_CONST")); + bool carry_set = get_param_or_def(cell.second.get(), ctx->id("CIN_SET")); + if (carry_const) { + if (!ctx->force) + NPNR_ASSERT(z == 0); + set_config(ti, config.at(y).at(x), "CarryInSet", carry_set); + } + } else if (cell.second->type == ctx->id("SB_IO")) { + const BelInfoPOD &beli = ci.bel_data[bel.index]; + int x = beli.x, y = beli.y, z = beli.z; + const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO]; + unsigned pin_type = get_param_or_def(cell.second.get(), ctx->id("PIN_TYPE")); + bool neg_trigger = get_param_or_def(cell.second.get(), ctx->id("NEG_TRIGGER")); + bool pullup = get_param_or_def(cell.second.get(), ctx->id("PULLUP")); + for (int i = 0; i < 6; i++) { + bool val = (pin_type >> i) & 0x01; + set_config(ti, config.at(y).at(x), "IOB_" + std::to_string(z) + ".PINTYPE_" + std::to_string(i), val); + } + set_config(ti, config.at(y).at(x), "NegClk", neg_trigger); + auto ieren = get_ieren(bi, x, y, z); + int iex, iey, iez; + std::tie(iex, iey, iez) = ieren; + NPNR_ASSERT(iez != -1); + + bool input_en = false; + if ((ctx->wire_to_net[ctx->getWireBelPin(bel, PIN_D_IN_0).index] != IdString()) || + (ctx->wire_to_net[ctx->getWireBelPin(bel, PIN_D_IN_1).index] != IdString())) { + input_en = true; + } + + if (ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K) { + set_config(ti, config.at(iey).at(iex), "IoCtrl.IE_" + std::to_string(iez), !input_en); + set_config(ti, config.at(iey).at(iex), "IoCtrl.REN_" + std::to_string(iez), !pullup); + } else { + set_config(ti, config.at(iey).at(iex), "IoCtrl.IE_" + std::to_string(iez), input_en); + set_config(ti, config.at(iey).at(iex), "IoCtrl.REN_" + std::to_string(iez), !pullup); + } + + if (ctx->args.type == ArchArgs::UP5K) { + if (iez == 0) { + set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_39", !pullup); + } else if (iez == 1) { + set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_35", !pullup); + } + } + } else if (cell.second->type == ctx->id("SB_GB")) { + // no cell config bits + } else if (cell.second->type == ctx->id("ICESTORM_RAM")) { + const BelInfoPOD &beli = ci.bel_data[bel.index]; + int x = beli.x, y = beli.y; + const TileInfoPOD &ti_ramt = bi.tiles_nonrouting[TILE_RAMT]; + const TileInfoPOD &ti_ramb = bi.tiles_nonrouting[TILE_RAMB]; + if (!(ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K)) { + set_config(ti_ramb, config.at(y).at(x), "RamConfig.PowerUp", true); + } + bool negclk_r = get_param_or_def(cell.second.get(), ctx->id("NEG_CLK_R")); + bool negclk_w = get_param_or_def(cell.second.get(), ctx->id("NEG_CLK_W")); + int write_mode = get_param_or_def(cell.second.get(), ctx->id("WRITE_MODE")); + int read_mode = get_param_or_def(cell.second.get(), ctx->id("READ_MODE")); + set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w); + set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r); + + set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_0", write_mode & 0x1); + set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_1", write_mode & 0x2); + set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_2", read_mode & 0x1); + set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_3", read_mode & 0x2); + } else if (cell.second->type == ctx->id("SB_WARMBOOT") || cell.second->type == ctx->id("ICESTORM_LFOSC")) { + // No config needed + } else if (cell.second->type == ctx->id("ICESTORM_SPRAM")) { + const BelInfoPOD &beli = ci.bel_data[bel.index]; + int x = beli.x, y = beli.y, z = beli.z; + NPNR_ASSERT(ctx->args.type == ArchArgs::UP5K); + if (x == 0 && y == 0) { + const TileInfoPOD &ti_ipcon = bi.tiles_nonrouting[TILE_IPCON]; + if (z == 1) { + set_config(ti_ipcon, config.at(1).at(0), "IpConfig.CBIT_0", true); + } else if (z == 2) { + set_config(ti_ipcon, config.at(1).at(0), "IpConfig.CBIT_1", true); + } else { + NPNR_ASSERT(false); + } + } else if (x == 25 && y == 0) { + const TileInfoPOD &ti_ipcon = bi.tiles_nonrouting[TILE_IPCON]; + if (z == 3) { + set_config(ti_ipcon, config.at(1).at(25), "IpConfig.CBIT_0", true); + } else if (z == 4) { + set_config(ti_ipcon, config.at(1).at(25), "IpConfig.CBIT_1", true); + } else { + NPNR_ASSERT(false); + } + } + } else if (cell.second->type == ctx->id("ICESTORM_DSP")) { + const std::vector> mac16_params = {{"C_REG", 1}, + {"A_REG", 1}, + {"B_REG", 1}, + {"D_REG", 1}, + {"TOP_8x8_MULT_REG", 1}, + {"BOT_8x8_MULT_REG", 1}, + {"PIPELINE_16x16_MULT_REG1", 1}, + {"PIPELINE_16x16_MULT_REG2", 1}, + {"TOPOUTPUT_SELECT", 2}, + {"TOPADDSUB_LOWERINPUT", 2}, + {"TOPADDSUB_UPPERINPUT", 1}, + {"TOPADDSUB_CARRYSELECT", 2}, + {"BOTOUTPUT_SELECT", 2}, + {"BOTADDSUB_LOWERINPUT", 2}, + {"BOTADDSUB_UPPERINPUT", 1}, + {"BOTADDSUB_CARRYSELECT", 2}, + {"MODE_8x8", 1}, + {"A_SIGNED", 1}, + {"B_SIGNED", 1}}; + configure_extra_cell(config, ctx, cell.second.get(), mac16_params, false); + } else { + NPNR_ASSERT(false); + } + } + // Set config bits in unused IO and RAM + for (auto bel : ctx->getBels()) { + if (ctx->bel_to_cell[bel.index] == IdString() && ctx->getBelType(bel) == TYPE_SB_IO) { + const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO]; + const BelInfoPOD &beli = ci.bel_data[bel.index]; + int x = beli.x, y = beli.y, z = beli.z; + auto ieren = get_ieren(bi, x, y, z); + int iex, iey, iez; + std::tie(iex, iey, iez) = ieren; + if (iez != -1) { + if (ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K) { + set_config(ti, config.at(iey).at(iex), "IoCtrl.IE_" + std::to_string(iez), true); + set_config(ti, config.at(iey).at(iex), "IoCtrl.REN_" + std::to_string(iez), false); + } + } + } else if (ctx->bel_to_cell[bel.index] == IdString() && ctx->getBelType(bel) == TYPE_ICESTORM_RAM) { + const BelInfoPOD &beli = ci.bel_data[bel.index]; + int x = beli.x, y = beli.y; + const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_RAMB]; + if ((ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K)) { + set_config(ti, config.at(y).at(x), "RamConfig.PowerUp", true); + } + } + } + + // Set other config bits + for (int y = 0; y < ci.height; y++) { + for (int x = 0; x < ci.width; x++) { + TileType tile = tile_at(ctx, x, y); + const TileInfoPOD &ti = bi.tiles_nonrouting[tile]; + + // set all ColBufCtrl bits (FIXME) + bool setColBufCtrl = true; + if (ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K) { + if (tile == TILE_RAMB || tile == TILE_RAMT) { + setColBufCtrl = (y == 3 || y == 5 || y == 11 || y == 13); + } else { + setColBufCtrl = (y == 4 || y == 5 || y == 12 || y == 13); + } + } else if (ctx->args.type == ArchArgs::LP8K || ctx->args.type == ArchArgs::HX8K) { + setColBufCtrl = (y == 8 || y == 9 || y == 24 || y == 25); + } else if (ctx->args.type == ArchArgs::UP5K) { + setColBufCtrl = (y == 4 || y == 5 || y == 14 || y == 15 || y == 26 || y == 27); + } + if (setColBufCtrl) { + set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_0", true); + set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_1", true); + set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_2", true); + set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_3", true); + set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_4", true); + set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_5", true); + set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_6", true); + set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_7", true); + } + + // Weird UltraPlus bits + if (tile == TILE_DSP0 || tile == TILE_DSP1 || tile == TILE_DSP2 || tile == TILE_DSP3 || + tile == TILE_IPCON) { + if (ctx->args.type == ArchArgs::UP5K && x == 25 && y == 14) { + // Mystery bits not set in this one tile + } else { + for (int lc_idx = 0; lc_idx < 8; lc_idx++) { + static const std::vector ip_dsp_lut_perm = { + 4, 14, 15, 5, 6, 16, 17, 7, 3, 13, 12, 2, 1, 11, 10, 0, + }; + for (int i = 0; i < 16; i++) + set_config(ti, config.at(y).at(x), "LC_" + std::to_string(lc_idx), ((i % 8) >= 4), + ip_dsp_lut_perm.at(i)); + if (tile == TILE_IPCON) + set_config(ti, config.at(y).at(x), + "Cascade.IPCON_LC0" + std::to_string(lc_idx) + "_inmux02_5", true); + else + set_config(ti, config.at(y).at(x), + "Cascade.MULT" + std::to_string(int(tile - TILE_DSP0)) + "_LC0" + + std::to_string(lc_idx) + "_inmux02_5", + true); + } + } + } + } + } + + // Write config out + for (int y = 0; y < ci.height; y++) { + for (int x = 0; x < ci.width; x++) { + TileType tile = tile_at(ctx, x, y); + out << tagTileType(tile); + out << " " << x << " " << y << std::endl; + for (auto row : config.at(y).at(x)) { + for (auto col : row) { + if (col == 1) + out << "1"; + else + out << "0"; + } + out << std::endl; + } + out << std::endl; + } + } + + // Write RAM init data + for (auto &cell : ctx->cells) { + if (cell.second->bel != BelId()) { + if (cell.second->type == ctx->id("ICESTORM_RAM")) { + const BelInfoPOD &beli = ci.bel_data[cell.second->bel.index]; + int x = beli.x, y = beli.y; + out << ".ram_data " << x << " " << y << std::endl; + for (int w = 0; w < 16; w++) { + std::vector bits(256); + std::string init = + get_param_str_or_def(cell.second.get(), ctx->id(std::string("INIT_") + get_hexdigit(w))); + NPNR_ASSERT(init != ""); + for (size_t i = 0; i < init.size(); i++) { + bool val = (init.at((init.size() - 1) - i) == '1'); + bits.at(i) = val; + } + for (int i = bits.size() - 4; i >= 0; i -= 4) { + int c = bits.at(i) + (bits.at(i + 1) << 1) + (bits.at(i + 2) << 2) + (bits.at(i + 3) << 3); + out << char(std::tolower(get_hexdigit(c))); + } + out << std::endl; + } + out << std::endl; + } + } + } + + // Write symbols + // const bool write_symbols = 1; + for (auto wire : ctx->getWires()) { + IdString net = ctx->getBoundWireNet(wire); + if (net != IdString()) + out << ".sym " << wire.index << " " << net.str(ctx) << std::endl; + } +} + +void read_config(Context *ctx, std::istream &in, chipconfig_t &config) +{ + constexpr size_t line_buf_size = 65536; + char buffer[line_buf_size]; + int tile_x = -1, tile_y = -1, line_nr = -1; + + while (1) { + in.getline(buffer, line_buf_size); + if (buffer[0] == '.') { + line_nr = -1; + const char *tok = strtok(buffer, " \t\r\n"); + + if (!strcmp(tok, ".device")) { + std::string config_device = strtok(nullptr, " \t\r\n"); + std::string expected; + switch (ctx->args.type) { + case ArchArgs::LP384: + expected = "384"; + break; + case ArchArgs::HX1K: + case ArchArgs::LP1K: + expected = "1k"; + break; + case ArchArgs::HX8K: + case ArchArgs::LP8K: + expected = "8k"; + break; + case ArchArgs::UP5K: + expected = "5k"; + break; + default: + log_error("unsupported device type\n"); + } + if (expected != config_device) + log_error("device type does not match\n"); + } else if (!strcmp(tok, ".io_tile") || !strcmp(tok, ".logic_tile") || !strcmp(tok, ".ramb_tile") || + !strcmp(tok, ".ramt_tile") || !strcmp(tok, ".ipcon_tile") || !strcmp(tok, ".dsp0_tile") || + !strcmp(tok, ".dsp1_tile") || !strcmp(tok, ".dsp2_tile") || !strcmp(tok, ".dsp3_tile")) { + line_nr = 0; + tile_x = atoi(strtok(nullptr, " \t\r\n")); + tile_y = atoi(strtok(nullptr, " \t\r\n")); + + TileType tile = tile_at(ctx, tile_x, tile_y); + if (tok != tagTileType(tile)) + log_error("Wrong tile type for specified position\n"); + + } else if (!strcmp(tok, ".extra_bit")) { + /* + int b = atoi(strtok(nullptr, " \t\r\n")); + int x = atoi(strtok(nullptr, " \t\r\n")); + int y = atoi(strtok(nullptr, " \t\r\n")); + std::tuple key(b, x, y); + extra_bits.insert(key); + */ + } else if (!strcmp(tok, ".sym")) { + int wireIndex = atoi(strtok(nullptr, " \t\r\n")); + const char *name = strtok(nullptr, " \t\r\n"); + + std::unique_ptr created_net = std::unique_ptr(new NetInfo); + IdString netName = ctx->id(name); + created_net->name = netName; + ctx->nets[netName] = std::move(created_net); + + WireId wire; + wire.index = wireIndex; + ctx->bindWire(wire, netName, STRENGTH_WEAK); + } + } else if (line_nr >= 0 && strlen(buffer) > 0) { + if (line_nr > int(config.at(tile_y).at(tile_x).size() - 1)) + log_error("Invalid data in input asc file"); + for (int i = 0; buffer[i] == '0' || buffer[i] == '1'; i++) + config.at(tile_y).at(tile_x).at(line_nr).at(i) = (buffer[i] == '1') ? 1 : 0; + line_nr++; + } + if (in.eof()) + break; + } +} + +bool read_asc(Context *ctx, std::istream &in) +{ + try { + // [y][x][row][col] + const ChipInfoPOD &ci = *ctx->chip_info; + const BitstreamInfoPOD &bi = *ci.bits_info; + chipconfig_t config; + config.resize(ci.height); + for (int y = 0; y < ci.height; y++) { + config.at(y).resize(ci.width); + for (int x = 0; x < ci.width; x++) { + TileType tile = tile_at(ctx, x, y); + int rows = bi.tiles_nonrouting[tile].rows; + int cols = bi.tiles_nonrouting[tile].cols; + config.at(y).at(x).resize(rows, std::vector(cols)); + } + } + read_config(ctx, in, config); + return true; + } catch (log_execution_error_exception) { + return false; + } +} +NEXTPNR_NAMESPACE_END -- cgit v1.2.3 From 9f0be8cd5f90b6b471f7e19c393af14377b1dc0b Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 20 Jul 2018 19:16:36 +0200 Subject: make new context work again --- gui/designwidget.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gui/designwidget.cc b/gui/designwidget.cc index d28b843b..f7ae82f5 100644 --- a/gui/designwidget.cc +++ b/gui/designwidget.cc @@ -230,6 +230,9 @@ void DesignWidget::addToHistory(QTreeWidgetItem *item) void DesignWidget::newContext(Context *ctx) { treeWidget->clear(); + // reset pointers since they are not valid after clear + nets_root = nullptr; + cells_root = nullptr; history_ignore = false; history_index = -1; history.clear(); -- cgit v1.2.3 From 20941292ad06585524dd58afc57689ffb98297f3 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 21 Jul 2018 09:22:09 +0200 Subject: fix introduced bug --- ice40/bitstream.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 1acaad0e..924868b5 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -481,6 +481,8 @@ void write_asc(const Context *ctx, std::ostream &out) for (int y = 0; y < ci.height; y++) { for (int x = 0; x < ci.width; x++) { TileType tile = tile_at(ctx, x, y); + if (tile == TILE_NONE) + continue; out << tagTileType(tile); out << " " << x << " " << y << std::endl; for (auto row : config.at(y).at(x)) { -- cgit v1.2.3 From 1cd5c9dac8452ee8d8f51931dcff028245898618 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 21 Jul 2018 01:55:20 -0700 Subject: Update comment --- common/timing.cc | 118 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+) diff --git a/common/timing.cc b/common/timing.cc index 3a48935f..479dba26 100644 --- a/common/timing.cc +++ b/common/timing.cc @@ -22,6 +22,7 @@ #include #include #include "log.h" +#include "util.h" NEXTPNR_NAMESPACE_BEGIN @@ -114,4 +115,121 @@ void assign_budget(Context *ctx) log_info("Checksum: 0x%08x\n", ctx->checksum()); } +typedef std::unordered_map updates_t; +typedef std::unordered_map delays_t; + +static delay_t follow_net_update(Context *ctx, NetInfo *net, int path_length, delay_t slack, const delays_t& delays, updates_t& updates); + +// Follow a path, returning budget to annotate +static delay_t follow_user_port_update(Context *ctx, PortRef &user, int path_length, delay_t slack, const delays_t& delays, updates_t& updates) +{ + delay_t value; + if (ctx->getPortClock(user.cell, user.port) != IdString()) { + // At the end of a timing path (arguably, should check setup time + // here too) + value = slack / path_length; + } else { + // Default to the path ending here, if no further paths found + value = slack / path_length; + // Follow outputs of the user + for (auto& port : user.cell->ports) { + if (port.second.type == PORT_OUT) { + delay_t comb_delay; + // Look up delay through this path + bool is_path = ctx->getCellDelay(user.cell, user.port, port.first, comb_delay); + if (is_path) { + NetInfo *net = port.second.net; + if (net) { + delay_t path_budget = follow_net_update(ctx, net, path_length, slack - comb_delay, delays, updates); + value = std::min(value, path_budget); + } + } + } + } + } + + auto ret = updates.emplace(&user.cell->ports.at(user.port), value); + if (!ret.second && value < ret.first->second) { + ret.first->second = value; + } + return value; +} + +static delay_t follow_net_update(Context *ctx, NetInfo *net, int path_length, delay_t slack, const delays_t& delays,updates_t& updates) +{ + delay_t net_budget = slack / (path_length + 1); + for (auto& usr : net->users) { + net_budget = std::min(net_budget, follow_user_port_update(ctx, usr, path_length + 1, slack - get_or_default(delays, &usr.cell->ports.at(usr.port), 0.), delays, updates)); + } + return net_budget; +} + +void update_budget(Context *ctx) +{ + delays_t delays; + updates_t updates; + + // Compute the delay for every pin on every net + for (auto &n : ctx->nets) { + auto net = n.second.get(); + + int driver_x, driver_y; + bool driver_gb; + CellInfo *driver_cell = net->driver.cell; + if (!driver_cell) + continue; + if (driver_cell->bel == BelId()) + continue; + ctx->estimatePosition(driver_cell->bel, driver_x, driver_y, driver_gb); + WireId drv_wire = ctx->getWireBelPin(driver_cell->bel, ctx->portPinFromId(net->driver.port)); + if (driver_gb) + continue; + for (auto& load : net->users) { + if (load.cell == nullptr) + continue; + CellInfo *load_cell = load.cell; + if (load_cell->bel == BelId()) + continue; + WireId user_wire = ctx->getWireBelPin(load_cell->bel, ctx->portPinFromId(load.port)); + delay_t raw_wl = ctx->estimateDelay(drv_wire, user_wire); + delays.emplace(&load_cell->ports.at(load.port), raw_wl); + } + } + + // Go through all clocked drivers and distribute the available path slack evenly into every budget + for (auto &cell : ctx->cells) { + for (auto& port : cell.second->ports) { + if (port.second.type == PORT_OUT) { + IdString clock_domain = ctx->getPortClock(cell.second.get(), port.first); + if (clock_domain != IdString()) { + if (port.second.net) + follow_net_update(ctx, port.second.net, 0, delay_t(1.0e12 / ctx->target_freq) - get_or_default(delays, &port.second, 0.), delays, updates); + } + } + } + } + + // Update the budgets + for (auto &net : ctx->nets) { + for (auto& user : net.second->users) { + auto pi = &user.cell->ports.at(user.port); + auto it = updates.find(pi); + if (it == updates.end()) continue; + user.budget = delays.at(pi) + it->second; + + // Post-update check +// if (user.budget < 0) +// log_warning("port %s.%s, connected to net '%s', has negative " +// "timing budget of %fns\n", +// user.cell->name.c_str(ctx), user.port.c_str(ctx), net.first.c_str(ctx), +// ctx->getDelayNS(user.budget)); +// if (ctx->verbose) +// log_info("port %s.%s, connected to net '%s', has " +// "timing budget of %fns\n", +// user.cell->name.c_str(ctx), user.port.c_str(ctx), net.first.c_str(ctx), +// ctx->getDelayNS(user.budget)); + } + } +} + NEXTPNR_NAMESPACE_END -- cgit v1.2.3 From 241418dc250ba863add1ecddc0543bd00c915c0b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 21 Jul 2018 01:55:46 -0700 Subject: Add update_budget() to timing.h header --- common/timing.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/common/timing.h b/common/timing.h index 025e4a76..b5574392 100644 --- a/common/timing.h +++ b/common/timing.h @@ -27,6 +27,8 @@ NEXTPNR_NAMESPACE_BEGIN // Assign "budget" values for all user ports in the design void assign_budget(Context *ctx); +void update_budget(Context *ctx); + NEXTPNR_NAMESPACE_END #endif -- cgit v1.2.3 From d23cdd6c06a37ef32740ee910aba6704a8a46292 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 21 Jul 2018 01:59:16 -0700 Subject: Avoid hysteresis preventing placer from stopping --- common/placer1.cc | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/common/placer1.cc b/common/placer1.cc index 74a11040..be20c072 100644 --- a/common/placer1.cc +++ b/common/placer1.cc @@ -145,6 +145,7 @@ class SAPlacer } int n_no_progress = 0; + wirelen_t min_metric = curr_metric; double avg_metric = curr_metric; temp = 10000; @@ -169,6 +170,12 @@ class SAPlacer try_swap_position(cell, try_bel); } } + + if (curr_metric < min_metric) { + min_metric = curr_metric; + improved = true; + } + // Heuristic to improve placement on the 8k if (improved) n_no_progress = 0; @@ -222,6 +229,9 @@ class SAPlacer ctx->shuffle(autoplaced); assign_budget(ctx); } + else { + update_budget(ctx); + } // Recalculate total metric entirely to avoid rounding errors // accumulating over time @@ -365,8 +375,8 @@ class SAPlacer // SA acceptance criterea if (delta < 0 || (temp > 1e-6 && (ctx->rng() / float(0x3fffffff)) <= std::exp(-delta / temp))) { n_accept++; - if (delta < 2) - improved = true; + //if (delta < 2) + // improved = true; } else { if (other != IdString()) ctx->unbindBel(oldBel); -- cgit v1.2.3 From bbb140c6991f01838009a65c81399694fe8afe3f Mon Sep 17 00:00:00 2001 From: David Shah Date: Sat, 21 Jul 2018 11:52:41 +0200 Subject: Quick hack to route nets with lowest budget first --- common/router1.cc | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/common/router1.cc b/common/router1.cc index 94c7070e..50022169 100644 --- a/common/router1.cc +++ b/common/router1.cc @@ -402,6 +402,21 @@ struct Router NEXTPNR_NAMESPACE_BEGIN +static void prioritise_nets(Context *ctx, std::vector &netsArray) +{ + std::unordered_map netScores; + for (auto net_name : netsArray) { + delay_t score = std::numeric_limits::max(); + for (const auto &sink : ctx->nets.at(net_name)->users) { + if (sink.budget < score) + score = sink.budget; + } + netScores[net_name] = score; + } + std::sort(netsArray.begin(), netsArray.end(), + [&netScores](IdString a, IdString b) { return netScores[a] < netScores[b]; }); +} + bool router1(Context *ctx) { try { @@ -508,7 +523,7 @@ bool router1(Context *ctx) bool printNets = ctx->verbose && (netsQueue.size() < 10); std::vector netsArray(netsQueue.begin(), netsQueue.end()); - ctx->sorted_shuffle(netsArray); + prioritise_nets(ctx, netsArray); netsQueue.clear(); for (auto net_name : netsArray) { @@ -560,7 +575,7 @@ bool router1(Context *ctx) int ripCnt = 0; std::vector ripupArray(ripupQueue.begin(), ripupQueue.end()); - ctx->sorted_shuffle(ripupArray); + prioritise_nets(ctx, ripupArray); for (auto net_name : ripupArray) { if (printNets) -- cgit v1.2.3 From b2452f4646bd828a34ce9efe8ad0fb0772723a90 Mon Sep 17 00:00:00 2001 From: David Shah Date: Sat, 21 Jul 2018 19:33:42 +0200 Subject: HACK: set carry budgets to zero --- common/timing.cc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/common/timing.cc b/common/timing.cc index 479dba26..26f6530e 100644 --- a/common/timing.cc +++ b/common/timing.cc @@ -216,7 +216,10 @@ void update_budget(Context *ctx) auto it = updates.find(pi); if (it == updates.end()) continue; user.budget = delays.at(pi) + it->second; - + // HACK HACK HACK + if (net.second->driver.port == ctx->id("COUT")) + user.budget = 0; + // HACK HACK HACK // Post-update check // if (user.budget < 0) // log_warning("port %s.%s, connected to net '%s', has negative " -- cgit v1.2.3