From d5a032d00e83863222bc4f5407bb72c845697c1b Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 20 Jun 2018 13:10:40 +0200 Subject: Fix chipdb UltraPlus wires Signed-off-by: David Shah --- ice40/chipdb.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 67d24713..82b8be8b 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -124,7 +124,7 @@ def wire_type(name): wt = "LOCAL" elif name in ("OUT_ENB", "cen", "inclk", "latch", "outclk", "clk", "s_r", "carry_in", "carry_in_mux"): wt = "LOCAL" - elif name in ("in_0", "in_1", "in_2", "in_3", "cout", "lout", "out", "fabout"): + elif name in ("in_0", "in_1", "in_2", "in_3", "cout", "lout", "out", "fabout") or name.startswith("slf_op") or name.startswith("O_"): wt = "LOCAL" elif name.startswith("local_g") or name.startswith("glb2local_"): wt = "LOCAL" -- cgit v1.2.3