From c33aa259ad822d9c4ce3f46922504a70e730704c Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Sun, 8 Jul 2018 12:35:27 +0200
Subject: ecp5: Adding a simple prepacked synth script

Signed-off-by: David Shah <davey1576@gmail.com>
---
 ecp5/synth/.gitignore   |  0
 ecp5/synth/blinky.v     | 16 ++++++++++++
 ecp5/synth/blinky.ys    |  9 +++++++
 ecp5/synth/cells.v      | 39 ++++++++++++++++++++++++++++
 ecp5/synth/simple_map.v | 68 +++++++++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 132 insertions(+)
 create mode 100644 ecp5/synth/.gitignore
 create mode 100644 ecp5/synth/blinky.v
 create mode 100644 ecp5/synth/blinky.ys
 create mode 100644 ecp5/synth/cells.v
 create mode 100644 ecp5/synth/simple_map.v

diff --git a/ecp5/synth/.gitignore b/ecp5/synth/.gitignore
new file mode 100644
index 00000000..e69de29b
diff --git a/ecp5/synth/blinky.v b/ecp5/synth/blinky.v
new file mode 100644
index 00000000..aba58801
--- /dev/null
+++ b/ecp5/synth/blinky.v
@@ -0,0 +1,16 @@
+module top(input clk_pin, output [3:0] led_pin);
+
+	wire clk;
+	wire [3:0] led;
+
+	TRELLIS_IO #(.DIR("INPUT")) clk_buf (.B(clk_pin), .O(clk));
+	TRELLIS_IO #(.DIR("OUTPUT")) led_buf [3:0] (.B(led_pin), .I(led));
+
+	reg [25:0] ctr = 0;
+
+	always@(posedge clk)
+		ctr <= ctr + 1'b1;
+
+	assign led = ctr[25:22];
+
+endmodule
diff --git a/ecp5/synth/blinky.ys b/ecp5/synth/blinky.ys
new file mode 100644
index 00000000..c0b74636
--- /dev/null
+++ b/ecp5/synth/blinky.ys
@@ -0,0 +1,9 @@
+read_verilog blinky.v
+read_verilog -lib cells.v
+synth -top top
+abc -lut 4
+techmap -map simple_map.v
+splitnets
+opt_clean
+stat
+write_json blinky.json
diff --git a/ecp5/synth/cells.v b/ecp5/synth/cells.v
new file mode 100644
index 00000000..2435713a
--- /dev/null
+++ b/ecp5/synth/cells.v
@@ -0,0 +1,39 @@
+(* blackbox *)
+module TRELLIS_SLICE(
+	input A0, B0, C0, D0,
+	input A1, B1, C1, D1,
+	input M0, M1,
+	input FCI, FXA, FXB,
+	input CLK, LSR, CE,
+	output F0, Q0,
+	output F1, Q1,
+	output FCO, OFX0, OFX1
+);
+
+parameter MODE = "LOGIC";
+parameter GSR = "ENABLED";
+parameter SRMODE = "LSR_OVER_CE";
+parameter CEMUX = "1";
+parameter CLKMUX = "CLK";
+parameter LSRMUX = "LSR";
+parameter LUT0_INITVAL = 16'h0000;
+parameter LUT1_INITVAL = 16'h0000;
+parameter REG0_SD = "0";
+parameter REG1_SD = "0";
+parameter REG0_REGSET = "RESET";
+parameter REG1_REGSET = "RESET";
+parameter CCU2_INJECT1_0 = "NO";
+parameter CCU2_INJECT1_1 = "NO";
+
+endmodule
+
+(* blackbox *)
+module TRELLIS_IO(
+	inout B,
+	input I,
+	input T,
+	output O,
+);
+parameter DIR = "INPUT";
+
+endmodule
diff --git a/ecp5/synth/simple_map.v b/ecp5/synth/simple_map.v
new file mode 100644
index 00000000..4a50fd01
--- /dev/null
+++ b/ecp5/synth/simple_map.v
@@ -0,0 +1,68 @@
+module \$_DFF_P_ (input D, C, output Q);
+	TRELLIS_SLICE #(
+		.MODE("LOGIC"),
+		.CLKMUX("CLK"),
+		.CEMUX("1"),
+		.REG0_SD("0"),
+		.REG0_REGSET("RESET"),
+		.SRMODE("LSR_OVER_CE"),
+		.GSR("DISABLED")
+	) _TECHMAP_REPLACE_ (
+		.CLK(C),
+		.M0(D),
+		.Q0(Q)
+	);
+endmodule
+
+module \$lut (A, Y);
+	parameter WIDTH = 0;
+	parameter LUT = 0;
+
+	input [WIDTH-1:0] A;
+	output Y;
+
+	generate
+		if (WIDTH == 1) begin
+			TRELLIS_SLICE #(
+				.MODE("LOGIC"),
+				.LUT0_INITVAL(LUT)
+			) _TECHMAP_REPLACE_ (
+				.A0(A[0]),
+				.F0(Y)
+			);
+		end
+		if (WIDTH == 2) begin
+			TRELLIS_SLICE #(
+				.MODE("LOGIC"),
+				.LUT0_INITVAL(LUT)
+			) _TECHMAP_REPLACE_ (
+				.A0(A[0]),
+				.B0(A[1]),
+				.F0(Y)
+			);
+		end
+		if (WIDTH == 3) begin
+			TRELLIS_SLICE #(
+				.MODE("LOGIC"),
+				.LUT0_INITVAL(LUT)
+			) _TECHMAP_REPLACE_ (
+				.A0(A[0]),
+				.B0(A[1]),
+				.C0(A[2]),
+				.F0(Y)
+			);
+		end
+		if (WIDTH == 4) begin
+			TRELLIS_SLICE #(
+				.MODE("LOGIC"),
+				.LUT0_INITVAL(LUT)
+			) _TECHMAP_REPLACE_ (
+				.A0(A[0]),
+				.B0(A[1]),
+				.C0(A[2]),
+				.D0(A[3]),
+				.F0(Y)
+			);
+		end
+	endgenerate
+endmodule
-- 
cgit v1.2.3