From affc6da1af7afccba1da8cdf3b9e57a01b1fb5e5 Mon Sep 17 00:00:00 2001 From: David Shah Date: Sat, 4 Aug 2018 08:28:13 +0200 Subject: ice40: Add SB_GB timing to database Signed-off-by: David Shah --- ice40/chipdb.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/ice40/chipdb.py b/ice40/chipdb.py index a0d7f03c..d782013f 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -716,7 +716,9 @@ tmport_to_portpin = { "WCLKE": "WCLKE", "WE": "WE", "posedge:CLOCK": "CLOCK", - "posedge:SLEEP": "SLEEP" + "posedge:SLEEP": "SLEEP", + "USERSIGNALTOGLOBALBUFFER": "USER_SIGNAL_TO_GLOBAL_BUFFER", + "GLOBALBUFFEROUTPUT": "GLOBAL_BUFFER_OUTPUT" } for i in range(16): @@ -744,6 +746,8 @@ def add_cell_timingdata(bel_type, timing_cell, fast_db, slow_db): cell_timings[bel_type] = timing_entries add_cell_timingdata("ICESTORM_LC", "LogicCell40", fast_timings, slow_timings) +add_cell_timingdata("SB_GB", "ICE_GB", fast_timings, slow_timings) + if dev_name != "384": add_cell_timingdata("ICESTORM_RAM", "SB_RAM40_4K", fast_timings, slow_timings) if dev_name == "5k": -- cgit v1.2.3