From ad5e5f80ca4ad798d1afbddcae84e04f3a26f0e5 Mon Sep 17 00:00:00 2001 From: gatecat Date: Sun, 9 May 2021 18:28:49 +0100 Subject: mistral: Rename clock buffer primitive Signed-off-by: gatecat --- mistral/constids.inc | 2 +- mistral/globals.cc | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/mistral/constids.inc b/mistral/constids.inc index 2477f693..9450d8b1 100644 --- a/mistral/constids.inc +++ b/mistral/constids.inc @@ -75,4 +75,4 @@ X(VCC) X(LOC) -X(MISTRAL_CLKBUF) \ No newline at end of file +X(MISTRAL_CLKENA) \ No newline at end of file diff --git a/mistral/globals.cc b/mistral/globals.cc index 34e569d3..2d1b2ef8 100644 --- a/mistral/globals.cc +++ b/mistral/globals.cc @@ -28,9 +28,10 @@ void Arch::create_clkbuf(int x, int y) for (int z = 0; z < 4; z++) { // For now we only consider the input path from general routing, other inputs like dedicated clock pins are // still a TODO - BelId bel = add_bel(x, y, id(stringf("CLKBUF[%d]", z)), id_MISTRAL_CLKBUF); + BelId bel = add_bel(x, y, id(stringf("CLKBUF[%d]", z)), id_MISTRAL_CLKENA); add_bel_pin(bel, id_A, PORT_IN, get_port(CycloneV::CMUXHG, x, y, -1, CycloneV::CLKIN, z)); add_bel_pin(bel, id_Q, PORT_OUT, get_port(CycloneV::CMUXHG, x, y, z, CycloneV::CLKOUT)); + // TODO: enable pin } } -- cgit v1.2.3