From 92ef01830c9f92d1374b4d02965865f11fab0ccc Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 3 Dec 2020 11:40:00 +0000 Subject: ice40: Clarify feedback paths in PLL constraints code Signed-off-by: David Shah --- ice40/pack.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/ice40/pack.cc b/ice40/pack.cc index 1fc74ca5..7b03939a 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -1475,13 +1475,13 @@ void pack_plls(Context *ctx) // Determine dividers in VCO path vco_constr = input_constr / (int_or_default(packed->params, ctx->id("DIVF"), 0) + 1); divq = 1 << (int_or_default(packed->params, ctx->id("DIVQ"), 0)); - if (fbp_value != "1") + if (fbp_value != "1") // anything other than SIMPLE - feedback after DIVQ vco_constr /= divq; - if (fbp_value == "6") { + if (fbp_value == "6") { // EXTERNAL log_info(" Can't derive constraints for PLL '%s' in EXTERNAL feedback mode\n", ctx->nameOf(ci)); goto constr_fail; } - if (fbp_value == "2") { + if (fbp_value == "2") { // PHASE_AND_DELAY feedback - via shiftreg // Shiftreg divider is also in the VCO feedback path vco_constr /= sr_div; } -- cgit v1.2.3