From d1cc79bfc93c7f9009237db37adaa765f8a93744 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 30 Jul 2018 09:57:02 +0000 Subject: Update README.md --- README.md | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index dfe2af37..891e1314 100644 --- a/README.md +++ b/README.md @@ -6,6 +6,16 @@ range of real-world FPGA devices. It currently supports Lattice iCE40 devices and Lattice ECP5 devices, as well as a "generic" back-end for user-defined architectures. (ECP5 and "generic" support are still experimental.) +Currently nextpnr is beta software at best. But we aim at replacing +arachne-pnr as official place-and-route tool for the icestorm flow soon. + +Here is a screenshot of nextpnr for iCE40. Build instructions and getting +started notes can be found below. + + + + + Prerequisites ------------- @@ -144,9 +154,10 @@ Links and references - [Project X-Ray (Xilinx 7-Series)](https://symbiflow.github.io/prjxray-db/) - [Project Chibi (Intel MAX-V)](https://github.com/rqou/project-chibi) -### Other FOSS place and route tools (FPGA and ASIC) +### Other FOSS FPGA place and route projects - [Arachne PNR](https://github.com/cseed/arachne-pnr) - [VPR/VTR](https://verilogtorouting.org/) -- [graywolf/timberwolf](https://github.com/rubund/graywolf) -- [qrouter](http://opencircuitdesign.com/qrouter/) +- [SymbiFlow](https://github.com/SymbiFlow/symbiflow-arch-defs) +- [Gaffe](https://github.com/kc8apf/gaffe) +- [KinglerPAR](https://github.com/rqou/KinglerPAR) -- cgit v1.2.3 From 1cf9c678135799222746c9145179c05245815c42 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 30 Jul 2018 10:00:26 +0000 Subject: Update README.md --- README.md | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index 891e1314..51141b09 100644 --- a/README.md +++ b/README.md @@ -1,10 +1,11 @@ nextpnr -- a portable FPGA place and route tool =============================================== -nextpnr is an FPGA place and route tool with emphasis on supporting a wide -range of real-world FPGA devices. It currently supports Lattice iCE40 devices -and Lattice ECP5 devices, as well as a "generic" back-end for user-defined -architectures. (ECP5 and "generic" support are still experimental.) +nextpnr is an FPGA place and route tool with emphasis on supporting +timing-driven place and route for a wide range of real-world FPGA devices. +It currently supports Lattice iCE40 devices and Lattice ECP5 devices, +as well as a "generic" back-end for user-defined architectures. +(ECP5 and "generic" support are still experimental.) Currently nextpnr is beta software at best. But we aim at replacing arachne-pnr as official place-and-route tool for the icestorm flow soon. -- cgit v1.2.3 From 0db86b8619883c0cbaf36150c3622c9d78d82d12 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 30 Jul 2018 13:57:14 +0200 Subject: Improve ice40/benchmark Signed-off-by: Clifford Wolf --- ice40/benchmark/Makefile | 6 ++++-- ice40/benchmark/report.ipynb | 40 +++++++++++++++++++++++++++++++--------- 2 files changed, 35 insertions(+), 11 deletions(-) diff --git a/ice40/benchmark/Makefile b/ice40/benchmark/Makefile index 5e16d9b0..5a276b18 100644 --- a/ice40/benchmark/Makefile +++ b/ice40/benchmark/Makefile @@ -1,3 +1,5 @@ +SHELL = /bin/bash + reports:: define mkreport @@ -10,10 +12,10 @@ report_n$1.txt: hx8kdemo_n$1.asc icetime -m -r report_n$1.txt -d hx8k hx8kdemo_n$1.asc hx8kdemo_a$1.asc: hx8kdemo.blif - arachne-pnr -d 8k -p hx8kdemo.pcf -o hx8kdemo_a$1.asc -s 1$1 hx8kdemo.blif > hx8kdemo_a$1.log 2>&1 + { time arachne-pnr -d 8k -p hx8kdemo.pcf -o hx8kdemo_a$1.asc -s 1$1 hx8kdemo.blif; } > hx8kdemo_a$1.log 2>&1 hx8kdemo_n$1.asc: hx8kdemo.json - ../../nextpnr-ice40 --asc hx8kdemo_n$1.asc --json hx8kdemo.json --pcf hx8kdemo.pcf --hx8k --seed 1$1 > hx8kdemo_n$1.log 2>&1 + { time ../../nextpnr-ice40 --asc hx8kdemo_n$1.asc --json hx8kdemo.json --pcf hx8kdemo.pcf --hx8k --seed 1$1; } > hx8kdemo_n$1.log 2>&1 endef $(foreach i,0 1 2 3 4 5 6 7 8 9,$(eval $(call mkreport,$(i)))) diff --git a/ice40/benchmark/report.ipynb b/ice40/benchmark/report.ipynb index 3232f38c..b4e03283 100644 --- a/ice40/benchmark/report.ipynb +++ b/ice40/benchmark/report.ipynb @@ -11,36 +11,58 @@ "%matplotlib inline\n", "import numpy as np\n", "import matplotlib.pyplot as plt\n", - "import subprocess\n", + "import subprocess, re\n", "\n", "gitrev = subprocess.getoutput(\"git rev-parse --short HEAD\")\n", "\n", - "data_a = 1 + np.zeros(10)\n", - "data_n = 1 + np.zeros(10)\n", + "data_a = np.zeros((10, 2))\n", + "data_n = np.zeros((10, 2))\n", "\n", "for i in range(10):\n", " try:\n", " with open(\"report_a%d.txt\" % i, \"r\") as f:\n", " for line in f:\n", " if line.startswith(\"Total path delay:\"):\n", - " data_a[i] = float(line.split()[3])\n", + " data_a[i, 0] = float(line.split()[3])\n", " except:\n", - " pass\n", + " data_a[i, 0] = 1.0\n", + " \n", " try:\n", " with open(\"report_n%d.txt\" % i, \"r\") as f:\n", " for line in f:\n", " if line.startswith(\"Total path delay:\"):\n", - " data_n[i] = float(line.split()[3])\n", + " data_n[i, 0] = float(line.split()[3])\n", " except:\n", - " pass\n", + " data_n[i, 0] = 1.0\n", + " \n", + " with open(\"hx8kdemo_a%d.log\" % i, \"r\") as f:\n", + " for line in f:\n", + " match = re.match(r\"real\\s+(\\d+)m(\\d+)\", line)\n", + " if match:\n", + " data_a[i, 1] = float(match.group(1)) + float(match.group(2))/60\n", + " \n", + " with open(\"hx8kdemo_n%d.log\" % i, \"r\") as f:\n", + " for line in f:\n", + " match = re.match(r\"real\\s+(\\d+)m(\\d+)\", line)\n", + " if match:\n", + " data_n[i, 1] = float(match.group(1)) + float(match.group(2))/60\n", "\n", "plt.figure(figsize=(9,3))\n", "plt.title(\"nextpnr -- ice40/benchmark/ -- %s\" % gitrev)\n", - "plt.bar(np.arange(10), data_a, color='blue')\n", - "plt.bar(15+np.arange(10), data_n, color='red')\n", + "plt.bar(np.arange(10), data_a[:, 0], color='blue')\n", + "plt.bar(15+np.arange(10), data_n[:, 0], color='red')\n", "plt.ylabel('Longest path (ns)')\n", "plt.xticks([5, 20], [\"arachne-pnr\", \"nextpnr\"])\n", "plt.xlim(-2, 27)\n", + "plt.show()\n", + "\n", + "plt.figure(figsize=(9,3))\n", + "plt.title(\"nextpnr -- ice40/benchmark/ -- %s\" % gitrev)\n", + "plt.bar(np.arange(10), data_a[:, 1], color='blue')\n", + "plt.bar(15+np.arange(10), data_n[:, 1], color='red')\n", + "plt.ylabel('Runtime (minutes)')\n", + "plt.xticks([5, 20], [\"arachne-pnr\", \"nextpnr\"])\n", + "plt.xlim(-2, 27)\n", "plt.show()" ] } -- cgit v1.2.3 From b5f90d381481dc3658c408b162aa433e183f79f4 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 30 Jul 2018 15:20:50 +0200 Subject: cmake: Remove nextpnrpy so modules Signed-off-by: David Shah --- CMakeLists.txt | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 41bd4aab..4c222d71 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -182,12 +182,7 @@ foreach (family ${ARCH}) add_executable(nextpnr-${family} ${COMMON_FILES} ${${ufamily}_FILES}) install(TARGETS nextpnr-${family} RUNTIME DESTINATION bin) target_compile_definitions(nextpnr-${family} PRIVATE MAIN_EXECUTABLE) - - if (BUILD_PYTHON) - # Add the importable Python module target - PYTHON_ADD_MODULE(nextpnrpy_${family} ${COMMON_FILES} ${${ufamily}_FILES}) - endif() - + # Add any new per-architecture targets here if (BUILD_TESTS) aux_source_directory(tests/${family}/ ${ufamily}_TEST_FILES) @@ -210,10 +205,6 @@ foreach (family ${ARCH}) set(family_targets ${family_targets} nextpnr-${family}-test) endif() - if (BUILD_PYTHON) - set(family_targets ${family_targets} nextpnrpy_${family}) - endif() - # Include the family-specific CMakeFile include(${family}/family.cmake) foreach (target ${family_targets}) -- cgit v1.2.3 From 1cde20273a48b0716cf1b3206edaff716fc78097 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 30 Jul 2018 15:58:13 +0200 Subject: python: Remove obsolete python_mod_test.py Signed-off-by: David Shah --- python/python_mod_test.py | 7 ------- 1 file changed, 7 deletions(-) delete mode 100644 python/python_mod_test.py diff --git a/python/python_mod_test.py b/python/python_mod_test.py deleted file mode 100644 index e7a8de94..00000000 --- a/python/python_mod_test.py +++ /dev/null @@ -1,7 +0,0 @@ -# Run: PYTHONPATH=. python3 python/python_mod_test.py -from nextpnrpy_ice40 import Chip, ChipArgs, iCE40Type -args = ChipArgs() -args.type = iCE40Type.HX1K -chip = Chip(args) -for wire in chip.getWires(): - print(chip.getWireName(wire)) -- cgit v1.2.3 From edc6cf8b23d973aa45a8c22516e7222eb6001391 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 30 Jul 2018 16:13:02 +0200 Subject: ice40: Print legalisation statistics Signed-off-by: David Shah --- ice40/place_legaliser.cc | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/ice40/place_legaliser.cc b/ice40/place_legaliser.cc index 9fde179d..ba09e250 100644 --- a/ice40/place_legaliser.cc +++ b/ice40/place_legaliser.cc @@ -114,17 +114,55 @@ class PlacementLegaliser public: PlacementLegaliser(Context *ctx) : ctx(ctx){}; + void print_stats(const char *point) + { + float distance_sum = 0; + float max_distance = 0; + int moved_cells = 0; + for (auto orig : originalPositions) { + if (ctx->cells.at(orig.first)->bel == BelId()) + continue; + Loc newLoc = ctx->getBelLocation(ctx->cells.at(orig.first)->bel); + if (newLoc != orig.second) { + float distance = std::sqrt(std::pow(newLoc.x - orig.second.x, 2) + pow(newLoc.y - orig.second.y, 2)); + moved_cells++; + distance_sum += distance; + if (distance > max_distance) + max_distance = distance; + } + } + log_info(" moved %d cells (after %s)\n", moved_cells, point); + if (moved_cells > 0) { + log_info(" average distance %f\n", (distance_sum / moved_cells)); + log_info(" maximum distance %f\n", max_distance); + } + } + bool legalise() { log_info("Legalising design..\n"); + for (auto &cell : ctx->cells) { + CellInfo *ci = cell.second.get(); + if (!ctx->getBelGlobalBuf(ci->bel) && cell.second->type == ctx->id("ICESTORM_LC")) { + originalPositions[cell.first] = ctx->getBelLocation(ci->bel); + } + } init_logic_cells(); bool legalised_carries = legalise_carries(); if (!legalised_carries && !ctx->force) return false; + print_stats("carry legalisation"); legalise_others(); + print_stats("misc. cell legalisation"); legalise_logic_tiles(); + print_stats("logic cell legalisation"); bool replaced_cells = replace_cells(); + print_stats("cell replacement"); + ctx->assignArchInfo(); + + + return legalised_carries && replaced_cells; } @@ -501,6 +539,7 @@ class PlacementLegaliser Context *ctx; std::unordered_set rippedCells; std::unordered_set createdCells; + std::unordered_map originalPositions; // Go from X and Y position to logic cells, setting occupied to true if a Bel is unavailable std::vector>>> logic_bels; }; -- cgit v1.2.3 From 267970c01e02cc197c0d488cc455161402929b34 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 30 Jul 2018 16:18:49 +0200 Subject: ice40: Improving legalisation move statistics Signed-off-by: David Shah --- ice40/place_legaliser.cc | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/ice40/place_legaliser.cc b/ice40/place_legaliser.cc index ba09e250..0d14fb35 100644 --- a/ice40/place_legaliser.cc +++ b/ice40/place_legaliser.cc @@ -119,9 +119,12 @@ class PlacementLegaliser float distance_sum = 0; float max_distance = 0; int moved_cells = 0; + int unplaced_cells = 0; for (auto orig : originalPositions) { - if (ctx->cells.at(orig.first)->bel == BelId()) + if (ctx->cells.at(orig.first)->bel == BelId()) { + unplaced_cells++; continue; + } Loc newLoc = ctx->getBelLocation(ctx->cells.at(orig.first)->bel); if (newLoc != orig.second) { float distance = std::sqrt(std::pow(newLoc.x - orig.second.x, 2) + pow(newLoc.y - orig.second.y, 2)); @@ -131,7 +134,7 @@ class PlacementLegaliser max_distance = distance; } } - log_info(" moved %d cells (after %s)\n", moved_cells, point); + log_info(" moved %d cells, %d unplaced (after %s)\n", moved_cells, unplaced_cells, point); if (moved_cells > 0) { log_info(" average distance %f\n", (distance_sum / moved_cells)); log_info(" maximum distance %f\n", max_distance); -- cgit v1.2.3 From 8f9b031ef07140b2bde00d470336ba99a5bce78c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 30 Jul 2018 16:21:03 +0200 Subject: Add iCE40 fast/slow delay fields to chipdb Signed-off-by: Clifford Wolf --- ice40/arch.cc | 5 +++++ ice40/arch.h | 17 +++++++++++++++-- ice40/chipdb.py | 12 +++++++++--- 3 files changed, 29 insertions(+), 5 deletions(-) diff --git a/ice40/arch.cc b/ice40/arch.cc index 3803f842..93a49dde 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -141,18 +141,23 @@ Arch::Arch(ArchArgs args) : args(args) #ifdef ICE40_HX1K_ONLY if (args.type == ArchArgs::HX1K) { + fast_part = true; chip_info = get_chip_info(reinterpret_cast *>(chipdb_blob_1k)); } else { log_error("Unsupported iCE40 chip type.\n"); } #else if (args.type == ArchArgs::LP384) { + fast_part = false; chip_info = get_chip_info(reinterpret_cast *>(chipdb_blob_384)); } else if (args.type == ArchArgs::LP1K || args.type == ArchArgs::HX1K) { + fast_part = args.type == ArchArgs::HX1K; chip_info = get_chip_info(reinterpret_cast *>(chipdb_blob_1k)); } else if (args.type == ArchArgs::UP5K) { + fast_part = false; chip_info = get_chip_info(reinterpret_cast *>(chipdb_blob_5k)); } else if (args.type == ArchArgs::LP8K || args.type == ArchArgs::HX8K) { + fast_part = args.type == ArchArgs::HX8K; chip_info = get_chip_info(reinterpret_cast *>(chipdb_blob_8k)); } else { log_error("Unsupported iCE40 chip type.\n"); diff --git a/ice40/arch.h b/ice40/arch.h index 51cbe725..0243e978 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -66,7 +66,8 @@ NPNR_PACKED_STRUCT(struct BelPortPOD { NPNR_PACKED_STRUCT(struct PipInfoPOD { // RelPtr name; int32_t src, dst; - int32_t delay; + int32_t fast_delay; + int32_t slow_delay; int8_t x, y; int16_t src_seg, dst_seg; int16_t switch_mask; @@ -89,6 +90,9 @@ NPNR_PACKED_STRUCT(struct WireInfoPOD { int32_t num_segments; RelPtr segments; + int32_t fast_delay; + int32_t slow_delay; + int8_t x, y; WireType type; int8_t padding_0; @@ -344,6 +348,7 @@ struct ArchArgs struct Arch : BaseCtx { + bool fast_part; const ChipInfoPOD *chip_info; const PackageInfoPOD *package_info; @@ -524,6 +529,11 @@ struct Arch : BaseCtx DelayInfo getWireDelay(WireId wire) const { DelayInfo delay; + NPNR_ASSERT(wire != WireId()); + if (fast_part) + delay.delay = chip_info->wire_data[wire.index].fast_delay; + else + delay.delay = chip_info->wire_data[wire.index].slow_delay; return delay; } @@ -637,7 +647,10 @@ struct Arch : BaseCtx { DelayInfo delay; NPNR_ASSERT(pip != PipId()); - delay.delay = chip_info->pip_data[pip.index].delay; + if (fast_part) + delay.delay = chip_info->pip_data[pip.index].fast_delay; + else + delay.delay = chip_info->pip_data[pip.index].slow_delay; return delay; } diff --git a/ice40/chipdb.py b/ice40/chipdb.py index b6af8fcf..d020fedc 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -748,7 +748,8 @@ for wire in range(num_wires): pi = dict() pi["src"] = src pi["dst"] = wire - pi["delay"] = pipdelay(src, wire) + pi["fast_delay"] = pipdelay(src, wire) + pi["slow_delay"] = pipdelay(src, wire) pi["x"] = pip_xy[(src, wire)][0] pi["y"] = pip_xy[(src, wire)][1] pi["switch_mask"] = pip_xy[(src, wire)][2] @@ -772,7 +773,8 @@ for wire in range(num_wires): pi = dict() pi["src"] = wire pi["dst"] = dst - pi["delay"] = pipdelay(wire, dst) + pi["fast_delay"] = pipdelay(wire, dst) + pi["slow_delay"] = pipdelay(wire, dst) pi["x"] = pip_xy[(wire, dst)][0] pi["y"] = pip_xy[(wire, dst)][1] pi["switch_mask"] = pip_xy[(wire, dst)][2] @@ -891,6 +893,9 @@ for wire, info in enumerate(wireinfo): else: bba.u32(0, "segments") + bba.u32(0, "fast_delay") + bba.u32(0, "slow_delay") + bba.u8(info["x"], "x") bba.u8(info["y"], "y") bba.u8(wiretypes[wire_type(info["name"])], "type") @@ -923,7 +928,8 @@ for info in pipinfo: # bba.s("X%d/Y%d/%s->%s" % (info["x"], info["y"], src_segname, dst_segname), "name") bba.u32(info["src"], "src") bba.u32(info["dst"], "dst") - bba.u32(info["delay"], "delay") + bba.u32(info["fast_delay"], "fast_delay") + bba.u32(info["slow_delay"], "slow_delay") bba.u8(info["x"], "x") bba.u8(info["y"], "y") bba.u16(src_seg, "src_seg") -- cgit v1.2.3 From 3d8b0087c32c264f2e234c1e743a894f95215009 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 30 Jul 2018 16:33:49 +0200 Subject: Add ice40 chipdb.py --fast/--slow Signed-off-by: Clifford Wolf --- ice40/chipdb.py | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/ice40/chipdb.py b/ice40/chipdb.py index d020fedc..a382c805 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -9,6 +9,8 @@ parser = argparse.ArgumentParser(description="convert ICE40 chip database") parser.add_argument("filename", type=str, help="chipdb input filename") parser.add_argument("-p", "--portspins", type=str, help="path to portpins.inc") parser.add_argument("-g", "--gfxh", type=str, help="path to gfx.h") +parser.add_argument("--fast", type=str, help="path to timing data for fast part") +parser.add_argument("--slow", type=str, help="path to timing data for slow part") args = parser.parse_args() dev_name = None @@ -51,6 +53,9 @@ wiretypes = dict() gfx_wire_ids = dict() wire_segments = dict() +fast_timings = None +slow_timings = None + with open(args.portspins) as f: for line in f: line = line.replace("(", " ") @@ -77,6 +82,31 @@ with open(args.gfxh) as f: name = line.strip().rstrip(",") gfx_wire_ids[name] = idx +def read_timings(filename): + db = dict() + with open(filename) as f: + cell = None + for line in f: + line = line.split() + if len(line) == 0: + continue + if line[0] == "CELL": + cell = line[1] + if line[0] == "IOPATH": + key = "%s.%s.%s" % (cell, line[1], line[2]) + v1 = line[3].split(":")[2] + v2 = line[4].split(":")[2] + v1 = 0 if v1 == "*" else float(v1) + v2 = 0 if v2 == "*" else float(v2) + db[key] = max(v1, v2) + return db + +if args.fast is not None: + fast_timings = read_timings(args.fast) + +if args.slow is not None: + slow_timings = read_timings(args.fast) + beltypes["ICESTORM_LC"] = 1 beltypes["ICESTORM_RAM"] = 2 beltypes["SB_IO"] = 3 -- cgit v1.2.3 From 84e008292539ae34f6e69a26b426ccc248dbed98 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 30 Jul 2018 16:40:56 +0200 Subject: cmake: Set --fast and --slow chipdb.py arguments Signed-off-by: David Shah --- ice40/chipdb.py | 2 +- ice40/family.cmake | 25 +++++++++++++++++++++++-- 2 files changed, 24 insertions(+), 3 deletions(-) diff --git a/ice40/chipdb.py b/ice40/chipdb.py index a382c805..d7c9e2af 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -105,7 +105,7 @@ if args.fast is not None: fast_timings = read_timings(args.fast) if args.slow is not None: - slow_timings = read_timings(args.fast) + slow_timings = read_timings(args.slow) beltypes["ICESTORM_LC"] = 1 beltypes["ICESTORM_RAM"] = 2 diff --git a/ice40/family.cmake b/ice40/family.cmake index 75061f44..02d4b4d8 100644 --- a/ice40/family.cmake +++ b/ice40/family.cmake @@ -14,17 +14,28 @@ file(MAKE_DIRECTORY ice40/chipdbs/) add_library(ice40_chipdb OBJECT ice40/chipdbs/) target_compile_definitions(ice40_chipdb PRIVATE NEXTPNR_NAMESPACE=nextpnr_${family}) target_include_directories(ice40_chipdb PRIVATE ${family}/) + if (MSVC) target_sources(ice40_chipdb PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/ice40/resource/embed.cc) set_source_files_properties(${CMAKE_CURRENT_SOURCE_DIR}/ice40/resources/chipdb.rc PROPERTIES LANGUAGE RC) foreach (dev ${devices}) + if (dev EQUAL "5k") + set(OPT_FAST "") + set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings-up5k.txt) + elseif(dev EQUAL "384") + set(OPT_FAST "") + set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings-lp384.txt) + else() + set(OPT_FAST --fast ${ICEBOX_ROOT}/timings-hx${dev}.txt) + set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings-lp${dev}.txt) + endif() set(DEV_TXT_DB ${ICEBOX_ROOT}/chipdb-${dev}.txt) set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bba) set(DEV_CC_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bin) set(DEV_PORTS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ice40/portpins.inc) set(DEV_GFXH ${CMAKE_CURRENT_SOURCE_DIR}/ice40/gfx.h) add_custom_command(OUTPUT ${DEV_CC_BBA_DB} - COMMAND ${PYTHON_EXECUTABLE} ${DB_PY} -p ${DEV_PORTS_INC} -g ${DEV_GFXH} ${DEV_TXT_DB} > ${DEV_CC_BBA_DB} + COMMAND ${PYTHON_EXECUTABLE} ${DB_PY} -p ${DEV_PORTS_INC} -g ${DEV_GFXH} ${OPT_FAST} ${OPT_SLOW} ${DEV_TXT_DB} > ${DEV_CC_BBA_DB} DEPENDS ${DEV_TXT_DB} ${DB_PY} ) add_custom_command(OUTPUT ${DEV_CC_DB} @@ -40,13 +51,23 @@ if (MSVC) else() target_compile_options(ice40_chipdb PRIVATE -g0 -O0 -w) foreach (dev ${devices}) + if (dev EQUAL "5k") + set(OPT_FAST "") + set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_up5k.txt) + elseif(dev EQUAL "384") + set(OPT_FAST "") + set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp384.txt) + else() + set(OPT_FAST --fast ${ICEBOX_ROOT}/timings_hx${dev}.txt) + set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp${dev}.txt) + endif() set(DEV_TXT_DB ${ICEBOX_ROOT}/chipdb-${dev}.txt) set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bba) set(DEV_CC_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.cc) set(DEV_PORTS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ice40/portpins.inc) set(DEV_GFXH ${CMAKE_CURRENT_SOURCE_DIR}/ice40/gfx.h) add_custom_command(OUTPUT ${DEV_CC_BBA_DB} - COMMAND ${PYTHON_EXECUTABLE} ${DB_PY} -p ${DEV_PORTS_INC} -g ${DEV_GFXH} ${DEV_TXT_DB} > ${DEV_CC_BBA_DB}.new + COMMAND ${PYTHON_EXECUTABLE} ${DB_PY} -p ${DEV_PORTS_INC} -g ${DEV_GFXH} ${OPT_FAST} ${OPT_SLOW} ${DEV_TXT_DB} > ${DEV_CC_BBA_DB}.new COMMAND mv ${DEV_CC_BBA_DB}.new ${DEV_CC_BBA_DB} DEPENDS ${DEV_TXT_DB} ${DB_PY} ) -- cgit v1.2.3 From 66a5b99f02b41c415911a7f2e045d167699cd82f Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 30 Jul 2018 16:47:52 +0200 Subject: python: Remove more dead files Signed-off-by: David Shah --- python/functions.py | 21 --------------------- python/python_test.py | 2 -- 2 files changed, 23 deletions(-) delete mode 100644 python/functions.py delete mode 100644 python/python_test.py diff --git a/python/functions.py b/python/functions.py deleted file mode 100644 index 8d2e2fb8..00000000 --- a/python/functions.py +++ /dev/null @@ -1,21 +0,0 @@ -def get_drivers(wire): - wid = chip.getWireByName(wire) - assert not wid.nil(), "wire {} not found".format(wire) - bp = chip.getBelPinUphill(wid) - if not bp.bel.nil(): - print("Bel pin: {}.{}".format(chip.getBelName(bp.bel), str(bp.pin))) - for pip in sorted(chip.getPipsUphill(wid), key=lambda x: x.index): - print("Pip: {}".format(chip.getWireName(chip.getPipSrcWire(pip)))) - - -def get_loads(wire): - wid = chip.getWireByName(wire) - assert not wid.nil(), "wire {} not found".format(wire) - for bp in sorted(chip.getBelPinsDownhill(wid), key=lambda x: (x.bel.index, x.pin)): - print("Bel pin: {}.{}".format(chip.getBelName(bp.bel), str(bp.pin))) - for pip in sorted(chip.getPipsDownhill(wid), key=lambda x: x.index): - print("Pip: {}".format(chip.getWireName(chip.getPipDstWire(pip)))) - - -#get_drivers("12_14_lutff_7/in_3") -#get_loads("12_14_lutff_global/clk") diff --git a/python/python_test.py b/python/python_test.py deleted file mode 100644 index 31d066b2..00000000 --- a/python/python_test.py +++ /dev/null @@ -1,2 +0,0 @@ -for wire in chip.getWires(): - print(chip.getWireName(wire)) -- cgit v1.2.3 From b09183db3bf5b08c1a1151e044f9df5f6dc445d8 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 30 Jul 2018 16:59:30 +0200 Subject: Use DelayInfo for cell timing instead of delay_t Signed-off-by: David Shah --- common/timing.cc | 8 ++++---- ecp5/arch.cc | 2 +- ecp5/arch.h | 2 +- generic/arch.cc | 2 +- generic/arch.h | 2 +- ice40/arch.cc | 14 +++++++------- ice40/arch.h | 2 +- 7 files changed, 16 insertions(+), 16 deletions(-) diff --git a/common/timing.cc b/common/timing.cc index d91dea20..4486fc24 100644 --- a/common/timing.cc +++ b/common/timing.cc @@ -41,13 +41,13 @@ static delay_t follow_user_port(Context *ctx, PortRef &user, int path_length, de // Follow outputs of the user for (auto port : user.cell->ports) { if (port.second.type == PORT_OUT) { - delay_t comb_delay; + DelayInfo comb_delay; // Look up delay through this path bool is_path = ctx->getCellDelay(user.cell, user.port, port.first, comb_delay); if (is_path) { NetInfo *net = port.second.net; if (net) { - delay_t path_budget = follow_net(ctx, net, path_length, slack - comb_delay); + delay_t path_budget = follow_net(ctx, net, path_length, slack - comb_delay.maxDelay()); value = std::min(value, path_budget); } } @@ -88,9 +88,9 @@ void assign_budget(Context *ctx) IdString clock_domain = ctx->getPortClock(cell.second.get(), port.first); if (clock_domain != IdString()) { delay_t slack = delay_t(1.0e12 / ctx->target_freq); // TODO: clock constraints - delay_t clkToQ; + DelayInfo clkToQ; if (ctx->getCellDelay(cell.second.get(), clock_domain, port.first, clkToQ)) - slack -= clkToQ; + slack -= clkToQ.maxDelay(); if (port.second.net) follow_net(ctx, port.second.net, 0, slack); } diff --git a/ecp5/arch.cc b/ecp5/arch.cc index 55fe5704..c8617190 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -440,7 +440,7 @@ DecalXY Arch::getGroupDecal(GroupId pip) const { return {}; }; // ----------------------------------------------------------------------- -bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const +bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const { return false; } diff --git a/ecp5/arch.h b/ecp5/arch.h index b6aac9cf..7d183e11 100644 --- a/ecp5/arch.h +++ b/ecp5/arch.h @@ -801,7 +801,7 @@ struct Arch : BaseCtx // Get the delay through a cell from one port to another, returning false // if no path exists - bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const; + bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const; // Get the associated clock to a port, or empty if the port is combinational IdString getPortClock(const CellInfo *cell, IdString port) const; // Return true if a port is a clock diff --git a/generic/arch.cc b/generic/arch.cc index 5c9864ab..892bb0fd 100644 --- a/generic/arch.cc +++ b/generic/arch.cc @@ -425,7 +425,7 @@ DecalXY Arch::getGroupDecal(GroupId group) const { return groups.at(group).decal // --------------------------------------------------------------- -bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const +bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const { return false; } diff --git a/generic/arch.h b/generic/arch.h index 01a90ee1..ed069d4d 100644 --- a/generic/arch.h +++ b/generic/arch.h @@ -210,7 +210,7 @@ struct Arch : BaseCtx DecalXY getPipDecal(PipId pip) const; DecalXY getGroupDecal(GroupId group) const; - bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const; + bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const; IdString getPortClock(const CellInfo *cell, IdString port) const; bool isClockPort(const CellInfo *cell, IdString port) const; diff --git a/ice40/arch.cc b/ice40/arch.cc index 93a49dde..8162098c 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -775,29 +775,29 @@ std::vector Arch::getDecalGraphics(DecalId decal) const // ----------------------------------------------------------------------- -bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const +bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const { if (cell->type == id_icestorm_lc) { if ((fromPort == id_i0 || fromPort == id_i1 || fromPort == id_i2 || fromPort == id_i3) && (toPort == id_o || toPort == id_lo)) { - delay = 450; + delay.delay = 450; return true; } else if (fromPort == id_cin && toPort == id_cout) { - delay = 120; + delay.delay = 120; return true; } else if (fromPort == id_i1 && toPort == id_cout) { - delay = 260; + delay.delay = 260; return true; } else if (fromPort == id_i2 && toPort == id_cout) { - delay = 230; + delay.delay = 230; return true; } else if (fromPort == id_clk && toPort == id_o) { - delay = 540; + delay.delay = 540; return true; } } else if (cell->type == id_icestorm_ram) { if (fromPort == id_rclk) { - delay = 2140; + delay.delay = 2140; return true; } } diff --git a/ice40/arch.h b/ice40/arch.h index 0243e978..8c6a3d93 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -722,7 +722,7 @@ struct Arch : BaseCtx // Get the delay through a cell from one port to another, returning false // if no path exists - bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const; + bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const; // Get the associated clock to a port, or empty if the port is combinational IdString getPortClock(const CellInfo *cell, IdString port) const; // Return true if a port is a clock -- cgit v1.2.3 From b12100837239e5c874bf7f384307bf790317d0a3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 30 Jul 2018 17:17:07 +0200 Subject: Towards better ice40 timing data Signed-off-by: Clifford Wolf --- ice40/chipdb.py | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/ice40/chipdb.py b/ice40/chipdb.py index d7c9e2af..3ef58185 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -214,12 +214,18 @@ def wire_type(name): assert 0 return wt -def pipdelay(src, dst): +def pipdelay(src, dst, db): + if db is None: + return 0 + src = wire_names_r[src] dst = wire_names_r[dst] src_type = wire_type(src[2]) dst_type = wire_type(dst[2]) + if dst[2].startswith("local_"): + return db["LocalMux.I.O"] + if src_type == "LOCAL" and dst_type == "LOCAL": return 250 @@ -253,7 +259,15 @@ def pipdelay(src, dst): # print(src, dst, src_type, dst_type, file=sys.stderr) assert 0 +def wiredelay(wire, db): + if db is None: + return 0 + + wire = wire_names_r[wire] + wtype = wire_type(wire[2]) + # FIXME + return 0 def init_tiletypes(device): global num_tile_types, tile_sizes, tile_bits @@ -778,8 +792,8 @@ for wire in range(num_wires): pi = dict() pi["src"] = src pi["dst"] = wire - pi["fast_delay"] = pipdelay(src, wire) - pi["slow_delay"] = pipdelay(src, wire) + pi["fast_delay"] = pipdelay(src, wire, fast_timings) + pi["slow_delay"] = pipdelay(src, wire, slow_timings) pi["x"] = pip_xy[(src, wire)][0] pi["y"] = pip_xy[(src, wire)][1] pi["switch_mask"] = pip_xy[(src, wire)][2] @@ -803,8 +817,8 @@ for wire in range(num_wires): pi = dict() pi["src"] = wire pi["dst"] = dst - pi["fast_delay"] = pipdelay(wire, dst) - pi["slow_delay"] = pipdelay(wire, dst) + pi["fast_delay"] = pipdelay(wire, dst, fast_timings) + pi["slow_delay"] = pipdelay(wire, dst, slow_timings) pi["x"] = pip_xy[(wire, dst)][0] pi["y"] = pip_xy[(wire, dst)][1] pi["switch_mask"] = pip_xy[(wire, dst)][2] @@ -923,8 +937,8 @@ for wire, info in enumerate(wireinfo): else: bba.u32(0, "segments") - bba.u32(0, "fast_delay") - bba.u32(0, "slow_delay") + bba.u32(wiredelay(wire, fast_timings), "fast_delay") + bba.u32(wiredelay(wire, slow_timings), "slow_delay") bba.u8(info["x"], "x") bba.u8(info["y"], "y") -- cgit v1.2.3 From 7da64ee167d518641a479cad1b660c608fb3dede Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 30 Jul 2018 20:10:36 +0200 Subject: Implement simple search --- gui/designwidget.cc | 26 +++++++++++++++++++++----- gui/designwidget.h | 6 ++++++ gui/treemodel.cc | 15 +++++++++++++++ gui/treemodel.h | 1 + 4 files changed, 43 insertions(+), 5 deletions(-) diff --git a/gui/designwidget.cc b/gui/designwidget.cc index 5107fbee..e8c05ef9 100644 --- a/gui/designwidget.cc +++ b/gui/designwidget.cc @@ -51,10 +51,11 @@ DesignWidget::DesignWidget(QWidget *parent) : QWidget(parent), ctx(nullptr), sel propertyEditor->treeWidget()->setContextMenuPolicy(Qt::CustomContextMenu); propertyEditor->treeWidget()->setSelectionMode(QAbstractItemView::ExtendedSelection); - QLineEdit *lineEdit = new QLineEdit(); - lineEdit->setClearButtonEnabled(true); - lineEdit->addAction(QIcon(":/icons/resources/zoom.png"), QLineEdit::LeadingPosition); - lineEdit->setPlaceholderText("Search..."); + searchEdit = new QLineEdit(); + searchEdit->setClearButtonEnabled(true); + searchEdit->addAction(QIcon(":/icons/resources/zoom.png"), QLineEdit::LeadingPosition); + searchEdit->setPlaceholderText("Search..."); + connect(searchEdit, SIGNAL(returnPressed()), this, SLOT(onSearchInserted())); actionFirst = new QAction("", this); actionFirst->setIcon(QIcon(":/icons/resources/resultset_first.png")); @@ -123,7 +124,7 @@ DesignWidget::DesignWidget(QWidget *parent) : QWidget(parent), ctx(nullptr), sel topWidget->setLayout(vbox1); vbox1->setSpacing(5); vbox1->setContentsMargins(0, 0, 0, 0); - vbox1->addWidget(lineEdit); + vbox1->addWidget(searchEdit); vbox1->addWidget(treeView); QWidget *toolbarWidget = new QWidget(); @@ -714,4 +715,19 @@ void DesignWidget::onItemDoubleClicked(QTreeWidgetItem *item, int column) } void DesignWidget::onDoubleClicked(const QModelIndex &index) { Q_EMIT zoomSelected(); } + +void DesignWidget::onSearchInserted() +{ + if (currentSearch == searchEdit->text()) { + currentIndex++; + if (currentIndex >= currentSearchIndexes.size()) + currentIndex = 0; + } else { + currentSearch = searchEdit->text(); + currentSearchIndexes = treeModel->search(searchEdit->text()); + currentIndex = 0; + } + if (currentSearchIndexes.size() > 0 && currentIndex < currentSearchIndexes.size()) + selectionModel->setCurrentIndex(currentSearchIndexes.at(currentIndex), QItemSelectionModel::ClearAndSelect); +} NEXTPNR_NAMESPACE_END diff --git a/gui/designwidget.h b/gui/designwidget.h index 27ead589..535fd0c3 100644 --- a/gui/designwidget.h +++ b/gui/designwidget.h @@ -64,6 +64,7 @@ class DesignWidget : public QWidget void onSelectionChanged(const QItemSelection &selected, const QItemSelection &deselected); void onItemDoubleClicked(QTreeWidgetItem *item, int column); void onDoubleClicked(const QModelIndex &index); + void onSearchInserted(); public Q_SLOTS: void newContext(Context *ctx); void updateTree(); @@ -77,6 +78,7 @@ class DesignWidget : public QWidget QTreeView *treeView; QItemSelectionModel *selectionModel; ContextTreeModel *treeModel; + QLineEdit *searchEdit; QtVariantPropertyManager *variantManager; QtVariantPropertyManager *readOnlyManager; QtGroupPropertyManager *groupManager; @@ -98,6 +100,10 @@ class DesignWidget : public QWidget QColor highlightColors[8]; QMap highlightSelected; + + QString currentSearch; + QList currentSearchIndexes; + int currentIndex; }; NEXTPNR_NAMESPACE_END diff --git a/gui/treemodel.cc b/gui/treemodel.cc index 59391f02..d79e38de 100644 --- a/gui/treemodel.cc +++ b/gui/treemodel.cc @@ -326,4 +326,19 @@ Qt::ItemFlags ContextTreeModel::flags(const QModelIndex &index) const ContextTreeItem *node = nodeFromIndex(index); return Qt::ItemIsEnabled | (node->type() != ElementType::NONE ? Qt::ItemIsSelectable : Qt::NoItemFlags); } + +QList ContextTreeModel::search(QString text) +{ + QList list; + for (int i = 0; i < 6; i++) { + for (auto key : nameToItem[i].keys()) { + if (key.contains(text, Qt::CaseInsensitive)) { + list.append(indexFromNode(nameToItem[i].value(key))); + if (list.count() > 500) + break; // limit to 500 results + } + } + } + return list; +} NEXTPNR_NAMESPACE_END \ No newline at end of file diff --git a/gui/treemodel.h b/gui/treemodel.h index a85c290a..c14efa90 100644 --- a/gui/treemodel.h +++ b/gui/treemodel.h @@ -72,6 +72,7 @@ class ContextTreeModel : public QAbstractItemModel ContextTreeItem *nodeFromIndex(const QModelIndex &idx) const; QModelIndex indexFromNode(ContextTreeItem *node); ContextTreeItem *nodeForIdType(const ElementType type, const QString name) const; + QList search(QString text); // Override QAbstractItemModel methods int rowCount(const QModelIndex &parent = QModelIndex()) const Q_DECL_OVERRIDE; int columnCount(const QModelIndex &parent = QModelIndex()) const Q_DECL_OVERRIDE; -- cgit v1.2.3 From 32ff0059feeb2dd8187393c63dae7db59a2e5b43 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 31 Jul 2018 11:55:25 +0200 Subject: Add binary search to getBelPinWire() and getBelPinType() Signed-off-by: Clifford Wolf --- ice40/arch.cc | 43 ++++++++++++++++++++++++++++++++++++------- ice40/arch.h | 2 +- ice40/chipdb.py | 14 ++++++-------- 3 files changed, 43 insertions(+), 16 deletions(-) diff --git a/ice40/arch.cc b/ice40/arch.cc index 8162098c..fd68e972 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -311,9 +311,23 @@ PortType Arch::getBelPinType(BelId bel, PortPin pin) const int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires; const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get(); - for (int i = 0; i < num_bel_wires; i++) - if (bel_wires[i].port == pin) - return PortType(bel_wires[i].type); + if (num_bel_wires < 7) { + for (int i = 0; i < num_bel_wires; i++) { + if (bel_wires[i].port == pin) + return PortType(bel_wires[i].type); + } + } else { + int b = 0, e = num_bel_wires-1; + while (b <= e) { + int i = (b+e) / 2; + if (bel_wires[i].port == pin) + return PortType(bel_wires[i].type); + if (bel_wires[i].port > pin) + e = i-1; + else + b = i+1; + } + } return PORT_INOUT; } @@ -327,10 +341,25 @@ WireId Arch::getBelPinWire(BelId bel, PortPin pin) const int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires; const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get(); - for (int i = 0; i < num_bel_wires; i++) { - if (bel_wires[i].port == pin) { - ret.index = bel_wires[i].wire_index; - break; + if (num_bel_wires < 7) { + for (int i = 0; i < num_bel_wires; i++) { + if (bel_wires[i].port == pin) { + ret.index = bel_wires[i].wire_index; + break; + } + } + } else { + int b = 0, e = num_bel_wires-1; + while (b <= e) { + int i = (b+e) / 2; + if (bel_wires[i].port == pin) { + ret.index = bel_wires[i].wire_index; + break; + } + if (bel_wires[i].port > pin) + e = i-1; + else + b = i+1; } } diff --git a/ice40/arch.h b/ice40/arch.h index 8c6a3d93..1d68ec4a 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -44,9 +44,9 @@ template struct RelPtr }; NPNR_PACKED_STRUCT(struct BelWirePOD { - int32_t wire_index; PortPin port; int32_t type; + int32_t wire_index; }); NPNR_PACKED_STRUCT(struct BelInfoPOD { diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 3ef58185..32d3485f 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -492,13 +492,13 @@ def add_bel_input(bel, wire, port): if wire not in wire_belports: wire_belports[wire] = set() wire_belports[wire].add((bel, port)) - bel_wires[bel].append((wire, port, 0)) + bel_wires[bel].append((portpins[port], 0, wire)) def add_bel_output(bel, wire, port): if wire not in wire_belports: wire_belports[wire] = set() wire_belports[wire].add((bel, port)) - bel_wires[bel].append((wire, port, 1)) + bel_wires[bel].append((portpins[port], 1, wire)) def add_bel_lc(x, y, z): bel = len(bel_name) @@ -759,14 +759,12 @@ bba.post('NEXTPNR_NAMESPACE_END') bba.push("chipdb_blob_%s" % dev_name) bba.r("chip_info_%s" % dev_name, "chip_info") -index = 0 for bel in range(len(bel_name)): bba.l("bel_wires_%d" % bel, "BelWirePOD") - for i in range(len(bel_wires[bel])): - bba.u32(bel_wires[bel][i][0], "wire_index") - bba.u32(portpins[bel_wires[bel][i][1]], "port") - bba.u32(bel_wires[bel][i][2], "type") - index += 1 + for data in sorted(bel_wires[bel]): + bba.u32(data[0], "port") + bba.u32(data[1], "type") + bba.u32(data[2], "wire_index") bba.l("bel_data_%s" % dev_name, "BelInfoPOD") for bel in range(len(bel_name)): -- cgit v1.2.3 From e3a403fa2990602941ce756726488820182aff26 Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 31 Jul 2018 14:36:17 +0200 Subject: ecp5: Disable Pip list in GUI for now Signed-off-by: David Shah --- gui/treemodel.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/gui/treemodel.cc b/gui/treemodel.cc index d79e38de..d42dc401 100644 --- a/gui/treemodel.cc +++ b/gui/treemodel.cc @@ -141,6 +141,7 @@ void ContextTreeModel::loadData(Context *ctx) QMap pip_items; // Add pips to tree +#ifndef ARCH_ECP5 for (auto pip : ctx->getPips()) { auto id = ctx->getPipName(pip); QStringList items = QString(id.c_str(ctx)).split("/"); @@ -164,6 +165,7 @@ void ContextTreeModel::loadData(Context *ctx) parent = pip_items[name]; } } +#endif pip_root->sort(); nets_root = new ContextTreeItem("Nets"); @@ -341,4 +343,4 @@ QList ContextTreeModel::search(QString text) } return list; } -NEXTPNR_NAMESPACE_END \ No newline at end of file +NEXTPNR_NAMESPACE_END -- cgit v1.2.3 From f3127f7dfd33469d29010b611aafb715a33b3be2 Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 31 Jul 2018 14:39:37 +0200 Subject: ecp5: Add Bel graphics Signed-off-by: David Shah --- ecp5/arch.cc | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++++---- ecp5/archdefs.h | 13 +++++++++---- ecp5/gfx.h | 35 +++++++++++++++++++++++++++++++++++ ecp5/main.cc | 10 ++++++---- 4 files changed, 103 insertions(+), 12 deletions(-) create mode 100644 ecp5/gfx.h diff --git a/ecp5/arch.cc b/ecp5/arch.cc index c8617190..7f7079bf 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -21,6 +21,7 @@ #include #include #include +#include "gfx.h" #include "log.h" #include "nextpnr.h" #include "placer1.h" @@ -421,16 +422,64 @@ bool Arch::route() { return router1(getCtx()); } // ----------------------------------------------------------------------- -std::vector Arch::getDecalGraphics(DecalId decalId) const +std::vector Arch::getDecalGraphics(DecalId decal) const { std::vector ret; - // FIXME + + if (decal.type == DecalId::TYPE_FRAME) { + /* nothing */ + } + + if (decal.type == DecalId::TYPE_BEL) { + BelId bel; + bel.index = decal.z; + bel.location = decal.location; + int z = locInfo(bel)->bel_data[bel.index].z; + auto bel_type = getBelType(bel); + + if (bel_type == TYPE_TRELLIS_SLICE) { + GraphicElement el; + el.type = GraphicElement::TYPE_BOX; + el.style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE; + el.x1 = bel.location.x + logic_cell_x1; + el.x2 = bel.location.x + logic_cell_x2; + el.y1 = bel.location.y + logic_cell_y1 + (z)*logic_cell_pitch; + el.y2 = bel.location.y + logic_cell_y2 + (z)*logic_cell_pitch; + ret.push_back(el); + } + + if (bel_type == TYPE_TRELLIS_IO) { + GraphicElement el; + el.type = GraphicElement::TYPE_BOX; + el.style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE; + el.x1 = bel.location.x + logic_cell_x1; + el.x2 = bel.location.x + logic_cell_x2; + el.y1 = bel.location.y + logic_cell_y1 + (2 * z) * logic_cell_pitch; + el.y2 = bel.location.y + logic_cell_y2 + (2 * z + 1) * logic_cell_pitch; + ret.push_back(el); + } + } + return ret; } -DecalXY Arch::getFrameDecal() const { return {}; } +DecalXY Arch::getFrameDecal() const +{ + DecalXY decalxy; + decalxy.decal.type = DecalId::TYPE_FRAME; + decalxy.decal.active = true; + return decalxy; +} -DecalXY Arch::getBelDecal(BelId bel) const { return {}; } +DecalXY Arch::getBelDecal(BelId bel) const +{ + DecalXY decalxy; + decalxy.decal.type = DecalId::TYPE_BEL; + decalxy.decal.location = bel.location; + decalxy.decal.z = bel.index; + decalxy.decal.active = bel_to_cell.count(bel) && (bel_to_cell.at(bel) != IdString()); + return decalxy; +} DecalXY Arch::getWireDecal(WireId wire) const { return {}; } diff --git a/ecp5/archdefs.h b/ecp5/archdefs.h index 40442e1b..829db683 100644 --- a/ecp5/archdefs.h +++ b/ecp5/archdefs.h @@ -120,17 +120,21 @@ struct GroupId struct DecalId { - char type = 0; // Bel/Wire/Pip/Frame (b/w/p/f) + enum + { + TYPE_FRAME, + TYPE_BEL + } type; Location location; uint32_t z = 0; - + bool active = false; bool operator==(const DecalId &other) const { - return type == other.type && location == other.location && z == other.z; + return type == other.type && location == other.location && z == other.z && active == other.active; } bool operator!=(const DecalId &other) const { - return type != other.type || location != other.location || z != other.z; + return type != other.type || location != other.location || z != other.z || active != other.active; } }; @@ -200,6 +204,7 @@ template <> struct hash boost::hash_combine(seed, hash()(decal.type)); boost::hash_combine(seed, hash()(decal.location)); boost::hash_combine(seed, hash()(decal.z)); + boost::hash_combine(seed, hash()(decal.active)); return seed; } }; diff --git a/ecp5/gfx.h b/ecp5/gfx.h new file mode 100644 index 00000000..0290d2f6 --- /dev/null +++ b/ecp5/gfx.h @@ -0,0 +1,35 @@ +/* + * nextpnr -- Next Generation Place and Route + * + * Copyright (C) 2018 David Shah + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef ECP5_GFX_H +#define ECP5_GFX_H + +#include "nextpnr.h" + +NEXTPNR_NAMESPACE_BEGIN + +const float logic_cell_x1 = 0.76; +const float logic_cell_x2 = 0.95; +const float logic_cell_y1 = 0.05; +const float logic_cell_y2 = 0.15; +const float logic_cell_pitch = 0.125; + +NEXTPNR_NAMESPACE_END + +#endif diff --git a/ecp5/main.cc b/ecp5/main.cc index f2db74d7..90096855 100644 --- a/ecp5/main.cc +++ b/ecp5/main.cc @@ -100,16 +100,18 @@ int main(int argc, char *argv[]) } if (vm.count("help") || argc == 1) { - std::cout << boost::filesystem::basename(argv[0]) << " -- Next Generation Place and Route (git " - "sha1 " GIT_COMMIT_HASH_STR ")\n"; + std::cout << boost::filesystem::basename(argv[0]) + << " -- Next Generation Place and Route (git " + "sha1 " GIT_COMMIT_HASH_STR ")\n"; std::cout << "\n"; std::cout << options << "\n"; return argc != 1; } if (vm.count("version")) { - std::cout << boost::filesystem::basename(argv[0]) << " -- Next Generation Place and Route (git " - "sha1 " GIT_COMMIT_HASH_STR ")\n"; + std::cout << boost::filesystem::basename(argv[0]) + << " -- Next Generation Place and Route (git " + "sha1 " GIT_COMMIT_HASH_STR ")\n"; return 1; } -- cgit v1.2.3 From 38d7cc3b8502b494f2d28a6de16eb634f23b7777 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 31 Jul 2018 13:41:18 +0000 Subject: Update README.md --- README.md | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/README.md b/README.md index 51141b09..c22579ba 100644 --- a/README.md +++ b/README.md @@ -162,3 +162,8 @@ Links and references - [SymbiFlow](https://github.com/SymbiFlow/symbiflow-arch-defs) - [Gaffe](https://github.com/kc8apf/gaffe) - [KinglerPAR](https://github.com/rqou/KinglerPAR) + +> SymbiFlow is working with the Verilog to Routing tool to extend the current +research tool to support real architectures. VtR is strongly focused on +architecture research but having support for real architectures might enable +research nextpnr zu providing documentation and explanation. -- cgit v1.2.3 From 2652485a0118a2dff46b6547683c8b988ee3b619 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 31 Jul 2018 16:43:19 +0200 Subject: Use icestorm timing information Signed-off-by: Clifford Wolf --- ice40/chipdb.py | 69 +++++++++++++++++++++++++++++++++++---------------------- 1 file changed, 42 insertions(+), 27 deletions(-) diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 32d3485f..97ccbe48 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -214,56 +214,71 @@ def wire_type(name): assert 0 return wt -def pipdelay(src, dst, db): +def pipdelay(src_idx, dst_idx, db): if db is None: return 0 - src = wire_names_r[src] - dst = wire_names_r[dst] + src = wire_names_r[src_idx] + dst = wire_names_r[dst_idx] src_type = wire_type(src[2]) dst_type = wire_type(dst[2]) - if dst[2].startswith("local_"): - return db["LocalMux.I.O"] + if dst[2].startswith("sp4_") or dst[2].startswith("span4_"): + if src[2].startswith("sp12_") or src[2].startswith("span12_"): + return db["Sp12to4.I.O"] + + if src[2].startswith("span4_"): + return db["IoSpan4Mux.I.O"] + + if dst[2].startswith("sp4_h_"): + return db["Span4Mux_h4.I.O"] + else: + return db["Span4Mux_v4.I.O"] - if src_type == "LOCAL" and dst_type == "LOCAL": - return 250 + if dst[2].startswith("sp12_") or dst[2].startswith("span12_"): + if dst[2].startswith("sp12_h_"): + return db["Span12Mux_h12.I.O"] + else: + return db["Span12Mux_v12.I.O"] - if src_type == "GLOBAL" and dst_type == "LOCAL": - return 400 + if dst[2] in ("fabout", "clk"): + return 0 # FIXME? - # Local -> Span + if src[2].startswith("glb_netwk_") and dst[2].startswith("glb2local_"): + return 0 # FIXME? - if src_type == "LOCAL" and dst_type in ("SP4_HORZ", "SP4_VERT"): - return 350 + if dst[2] == "carry_in_mux": + return db["ICE_CARRY_IN_MUX.carryinitin.carryinitout"] - if src_type == "LOCAL" and dst_type in ("SP12_HORZ", "SP12_VERT"): - return 500 + if dst[2] in ("lutff_global/clk", "io_global/inclk", "io_global/outclk", "ram/RCLK", "ram/WCLK"): + return db["ClkMux.I.O"] - # Span -> Local + if dst[2] in ("lutff_global/s_r", "io_global/latch", "ram/RE", "ram/WE"): + return db["SRMux.I.O"] - if src_type in ("SP4_HORZ", "SP4_VERT", "SP12_HORZ", "SP12_VERT") and dst_type == "LOCAL": - return 300 + if dst[2] in ("lutff_global/cen", "io_global/cen", "ram/RCLKE", "ram/WCLKE"): + return db["CEMux.I.O"] - # Span -> Span + if dst[2].startswith("local_"): + return db["LocalMux.I.O"] - if src_type in ("SP12_HORZ", "SP12_VERT") and dst_type in ("SP12_HORZ", "SP12_VERT"): - return 450 + if src[2].startswith("local_") and dst[2] in ("io_0/D_OUT_0", "io_0/D_OUT_1", "io_0/OUT_ENB", "io_1/D_OUT_0", "io_1/D_OUT_1", "io_1/OUT_ENB"): + return db["IoInMux.I.O"] - if src_type in ("SP4_HORZ", "SP4_VERT") and dst_type in ("SP4_HORZ", "SP4_VERT"): - return 300 + if re.match(r"lutff_\d+/in_\d+", dst[2]): + return db["InMux.I.O"] - if src_type in ("SP12_HORZ", "SP12_VERT") and dst_type in ("SP4_HORZ", "SP4_VERT"): - return 380 + if re.match(r"ram/(MASK|RADDR|WADDR|WDATA)_", dst[2]): + return db["InMux.I.O"] - # print(src, dst, src_type, dst_type, file=sys.stderr) + print(src, dst, src_idx, dst_idx, src_type, dst_type, file=sys.stderr) assert 0 -def wiredelay(wire, db): +def wiredelay(wire_idx, db): if db is None: return 0 - wire = wire_names_r[wire] + wire = wire_names_r[wire_idx] wtype = wire_type(wire[2]) # FIXME -- cgit v1.2.3