From be8d3fd74dae297d79e41165c2141aadef3d6582 Mon Sep 17 00:00:00 2001 From: YRabbit Date: Sat, 26 Mar 2022 20:56:30 +1000 Subject: gowin: Consider the peculiarity of GW1BR-9C The GW1NR-9C chip ODDR implementation differs from all other supported chips by two suspicious inputs. Signed-off-by: YRabbit --- gowin/arch.cc | 15 +++++++++++++++ gowin/arch.h | 3 +++ gowin/constids.inc | 2 ++ gowin/pack.cc | 7 +++++++ 4 files changed, 27 insertions(+) diff --git a/gowin/arch.cc b/gowin/arch.cc index fa0a66a3..dc40b179 100644 --- a/gowin/arch.cc +++ b/gowin/arch.cc @@ -1158,6 +1158,21 @@ Arch::Arch(ArchArgs args) : args(args) snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this)); addBelInput(belname, id_CLK, id(buf)); + const PairPOD *xxx_port = pairLookup(bel->ports.get(), bel->num_ports, ID_XXX_VSS); + if (xxx_port != nullptr) { + ddr_has_extra_inputs = true; + portname = IdString(xxx_port->src_id); + snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this)); + addBelInput(belname, id_XXX_VSS, id(buf)); + } + xxx_port = pairLookup(bel->ports.get(), bel->num_ports, ID_XXX_VCC); + if (xxx_port != nullptr) { + ddr_has_extra_inputs = true; + portname = IdString(xxx_port->src_id); + snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this)); + addBelInput(belname, id_XXX_VCC, id(buf)); + } + if (oddrc) { portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_CE)->src_id); snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this)); diff --git a/gowin/arch.h b/gowin/arch.h index c8392e7e..bc29a59b 100644 --- a/gowin/arch.h +++ b/gowin/arch.h @@ -470,6 +470,9 @@ struct Arch : BaseArch void updateClockSpinesCache(IdString spine_id, IdString wire_id); void fixClockSpineDecals(void); + // XXX GW1N-9C DDR quirk + bool ddr_has_extra_inputs = false; + // Permissible combinations of modes in a single slice std::map dff_comp_mode; }; diff --git a/gowin/constids.inc b/gowin/constids.inc index b293293b..8159cc10 100644 --- a/gowin/constids.inc +++ b/gowin/constids.inc @@ -681,6 +681,8 @@ X(IOBJS) // IOLOGIC X(TX) +X(XXX_VSS) +X(XXX_VCC) X(OBUF_TYPE) X(SBUF) X(DBUF) diff --git a/gowin/pack.cc b/gowin/pack.cc index d31b4a84..28370a75 100644 --- a/gowin/pack.cc +++ b/gowin/pack.cc @@ -798,6 +798,13 @@ static void pack_iologic(Context *ctx) ci->attrs[id_IOBUF] = 1; } } + // if have XXX_ inputs connect them + if (ctx->ddr_has_extra_inputs) { + ci->addInput(id_XXX_VSS); + ci->connectPort(id_XXX_VSS, ctx->nets[ctx->id("$PACKER_GND_NET")].get()); + ci->addInput(id_XXX_VCC); + ci->connectPort(id_XXX_VCC, ctx->nets[ctx->id("$PACKER_VCC_NET")].get()); + } } break; default: break; -- cgit v1.2.3