From 2ace9b5ad3685043470154f88d7e410e553be726 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 13 Sep 2019 16:50:07 +0100 Subject: ecp5: Move clock constraints across IO and DCCA Signed-off-by: David Shah --- ecp5/pack.cc | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/ecp5/pack.cc b/ecp5/pack.cc index e610dfe5..509d33f3 100644 --- a/ecp5/pack.cc +++ b/ecp5/pack.cc @@ -377,6 +377,13 @@ class Ecp5Packer log_error("Pin B of %s '%s' connected to more than a single top level IO.\n", trio->type.c_str(ctx), trio->name.c_str(ctx)); if (net != nullptr) { + if (net->clkconstr != nullptr && trio->ports.count(ctx->id("O"))) { + NetInfo *onet = trio->ports.at(ctx->id("O")).net; + if (onet != nullptr && !onet->clkconstr) { + // Move clock constraint from IO pad to input buffer output + std::swap(net->clkconstr, onet->clkconstr); + } + } ctx->nets.erase(net->name); trio->ports.at(ctx->id("B")).net = nullptr; } @@ -2361,6 +2368,8 @@ class Ecp5Packer copy_constraint(ci, id_CLKI, id_CDIVX, ratio); } else if (ci->type == id_ECLKSYNCB || ci->type == id_TRELLIS_ECLKBUF) { copy_constraint(ci, id_ECLKI, id_ECLKO, 1); + } else if (ci->type == id_DCCA) { + copy_constraint(ci, id_CLKI, id_CLKO, 1); } else if (ci->type == id_EHXPLLL) { delay_t period_in; if (!get_period(ci, id_CLKI, period_in)) -- cgit v1.2.3 From 9e8976996e576414ac3402b8efa63cd7bd1a89bb Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 13 Sep 2019 16:59:41 +0100 Subject: ice40: Move clock constraints across SB_IO and SB_GB_IO Signed-off-by: David Shah --- ice40/pack.cc | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/ice40/pack.cc b/ice40/pack.cc index f411aeee..f5649e64 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -490,6 +490,26 @@ static void pack_io(Context *ctx) sb->type.c_str(ctx), sb->name.c_str(ctx)); if (net != nullptr) { + + if (net->clkconstr != nullptr) { + if (sb->ports.count(id_D_IN_0)) { + NetInfo *din0_net = sb->ports.at(id_D_IN_0).net; + if (din0_net != nullptr && !din0_net->clkconstr) { + // Copy clock constraint from IO pad to input buffer output + din0_net->clkconstr = + std::unique_ptr(new ClockConstraint(*net->clkconstr)); + } + } + if (is_sb_gb_io(ctx, sb) && sb->ports.count(id_GLOBAL_BUFFER_OUTPUT)) { + NetInfo *gb_net = sb->ports.at(id_GLOBAL_BUFFER_OUTPUT).net; + if (gb_net != nullptr && !gb_net->clkconstr) { + // Copy clock constraint from IO pad to global buffer output + gb_net->clkconstr = + std::unique_ptr(new ClockConstraint(*net->clkconstr)); + } + } + } + delete_nets.insert(net->name); sb->ports.at(ctx->id("PACKAGE_PIN")).net = nullptr; } -- cgit v1.2.3