From 2f509734dff676b7543a574b64a46be4224a5aa4 Mon Sep 17 00:00:00 2001 From: gatecat Date: Mon, 27 Feb 2023 10:38:25 +0100 Subject: fabulous: Misc improvements Signed-off-by: gatecat --- generic/viaduct/fabulous/constids.inc | 1 + generic/viaduct/fabulous/fabulous.cc | 6 ++++-- generic/viaduct/fabulous/fasm.cc | 19 +++++++++++++++++++ 3 files changed, 24 insertions(+), 2 deletions(-) diff --git a/generic/viaduct/fabulous/constids.inc b/generic/viaduct/fabulous/constids.inc index b7fe721d..861eedf2 100644 --- a/generic/viaduct/fabulous/constids.inc +++ b/generic/viaduct/fabulous/constids.inc @@ -115,3 +115,4 @@ X(_CONST1) X(_LUT_PERM) X(_LUT_PERM_IN) +X(I_reg) diff --git a/generic/viaduct/fabulous/fabulous.cc b/generic/viaduct/fabulous/fabulous.cc index d658ce24..00c8909b 100644 --- a/generic/viaduct/fabulous/fabulous.cc +++ b/generic/viaduct/fabulous/fabulous.cc @@ -102,7 +102,9 @@ struct FabulousImpl : ViaductAPI if (ci->type == id_FABULOUS_LC) { auto &lct = cell_tags.get(ci); if (lct.comb.carry_used) { - ctx->addCellTimingDelay(ci->name, id_Ci, id_Co, 1.0); + ctx->addCellTimingDelay(ci->name, id_Ci, id_Co, 0.2); + ctx->addCellTimingDelay(ci->name, ctx->id("I1"), id_Co, 1.0); + ctx->addCellTimingDelay(ci->name, ctx->id("I2"), id_Co, 1.0); } if (lct.ff.ff_used) { ctx->addCellTimingClock(ci->name, id_CLK); @@ -638,7 +640,7 @@ struct FabulousImpl : ViaductAPI delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override { - if (src_pin == id_Ci && dst_pin == id_Co) + if (src_pin == id_Co && dst_pin == id_Ci) return 0.5; auto driver_loc = ctx->getBelLocation(src_bel); diff --git a/generic/viaduct/fabulous/fasm.cc b/generic/viaduct/fabulous/fasm.cc index 159bb8ff..f1c0c648 100644 --- a/generic/viaduct/fabulous/fasm.cc +++ b/generic/viaduct/fabulous/fasm.cc @@ -223,6 +223,23 @@ struct FabFasmWriter } } + void write_iopass(const CellInfo *ci) + { + Loc loc = ctx->getBelLocation(ci->bel); + // We use 'nice' names based on function for the IOPass bels inside nextpnr + // but in the bitstream we need to use character names + NPNR_ASSERT(loc.z <= 26); + prefix = stringf("X%dY%d.%c.", loc.x, loc.y, 'A' + loc.z); + if (ci->params.count(id_I_reg)) { + uint64_t regval = int_or_default(ci->params, id_I_reg); + for (unsigned i = 0; i < 4; i++) { + if (regval & (1 << i)) + out << prefix << stringf("I%d_reg", i) << std::endl; + } + } + prefix = ""; + } + void write_cell(const CellInfo *ci) { out << stringf("# config for cell '%s'\n", ctx->nameOf(ci)) << std::endl; @@ -231,6 +248,8 @@ struct FabFasmWriter write_logic(ci); else if (ci->type == id_IO_1_bidirectional_frame_config_pass) write_io(ci); + else if (ci->type.in(id_InPass4_frame_config, id_OutPass4_frame_config)) + write_iopass(ci); else write_generic_cell(ci); // TODO: other cell types -- cgit v1.2.3