From 0b911e484cebd05cb57c1ce68bf1482a91db03ca Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Wed, 3 Feb 2021 14:48:49 -0800 Subject: Run "make clangformat". Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- fpga_interchange/arch.cc | 59 ++++++--------- fpga_interchange/arch.h | 177 ++++++++++++++++++-------------------------- fpga_interchange/archdefs.h | 8 +- fpga_interchange/main.cc | 4 +- 4 files changed, 100 insertions(+), 148 deletions(-) diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc index 2d1195b5..b7c83434 100644 --- a/fpga_interchange/arch.cc +++ b/fpga_interchange/arch.cc @@ -75,9 +75,9 @@ Arch::Arch(ArchArgs args) : args(args) } // Sanity check cell name ids. - const CellMapPOD & cell_map = *chip_info->cell_map; + const CellMapPOD &cell_map = *chip_info->cell_map; int32_t first_cell_id = cell_map.cell_names[0]; - for(size_t i = 0; i < cell_map.number_cells; ++i) { + for (size_t i = 0; i < cell_map.number_cells; ++i) { log_assert(cell_map.cell_names[i] == i + first_cell_id); } } @@ -115,7 +115,7 @@ void Arch::setup_byname() const BelId Arch::getBelByName(IdStringList name) const { BelId ret; - if(name.ids.size() != 2) { + if (name.ids.size() != 2) { return BelId(); } @@ -147,7 +147,7 @@ BelRange Arch::getBelsByTile(int x, int y) const br.b.chip = chip_info; br.e.chip = chip_info; - if(br.b != br.e) { + if (br.b != br.e) { ++br.e; } return br; @@ -164,7 +164,7 @@ WireId Arch::getBelPinWire(BelId bel, IdString pin) const const int32_t *wires = bel_data.wires.get(); int32_t wire_index = wires[pin_index]; - if(wire_index < 0) { + if (wire_index < 0) { // This BEL pin is not connected. return WireId(); } else { @@ -188,7 +188,7 @@ PortType Arch::getBelPinType(BelId bel, IdString pin) const WireId Arch::getWireByName(IdStringList name) const { WireId ret; - if(name.ids.size() != 2) { + if (name.ids.size() != 2) { return WireId(); } @@ -233,10 +233,7 @@ WireId Arch::getWireByName(IdStringList name) const } IdString Arch::getWireType(WireId wire) const { return id(""); } -std::vector> Arch::getWireAttrs(WireId wire) const -{ - return {}; -} +std::vector> Arch::getWireAttrs(WireId wire) const { return {}; } // ----------------------------------------------------------------------- @@ -250,7 +247,7 @@ PipId Arch::getPipByName(IdStringList name) const setup_byname(); - if(name.ids.size() == 3) { + if (name.ids.size() == 3) { // This is a Site PIP. IdString site_name = name.ids[0]; IdString belname = name.ids[1]; @@ -269,8 +266,7 @@ PipId Arch::getPipByName(IdStringList name) const NPNR_ASSERT(pin_index >= 0); for (int i = 0; i < tile_info.num_pips; i++) { - if (tile_info.pip_data[i].site == site && - tile_info.pip_data[i].bel == bel.index && + if (tile_info.pip_data[i].site == site && tile_info.pip_data[i].bel == bel.index && tile_info.pip_data[i].extra_data == pin_index) { PipId ret; @@ -292,14 +288,13 @@ PipId Arch::getPipByName(IdStringList name) const std::string pip_second = name.ids[1].str(this); auto split = pip_second.find('.'); - if(split == std::string::npos) { + if (split == std::string::npos) { // This is a site pin! BelId bel = getBelByName(name); NPNR_ASSERT(bel != BelId()); for (int i = 0; i < tile_info.num_pips; i++) { - if (tile_info.pip_data[i].site == site && - tile_info.pip_data[i].bel == bel.index) { + if (tile_info.pip_data[i].site == site && tile_info.pip_data[i].bel == bel.index) { PipId ret; ret.tile = tile; @@ -310,20 +305,20 @@ PipId Arch::getPipByName(IdStringList name) const } else { // This is a psuedo site pip! IdString src_site_wire = id(pip_second.substr(0, split)); - IdString dst_site_wire = id(pip_second.substr(split+1)); + IdString dst_site_wire = id(pip_second.substr(split + 1)); int32_t src_index = -1; int32_t dst_index = -1; for (int i = 0; i < tile_info.num_wires; i++) { if (tile_info.wire_data[i].site == site && tile_info.wire_data[i].name == src_site_wire.index) { src_index = i; - if(dst_index != -1) { + if (dst_index != -1) { break; } } if (tile_info.wire_data[i].site == site && tile_info.wire_data[i].name == dst_site_wire.index) { dst_index = i; - if(src_index != -1) { + if (src_index != -1) { break; } } @@ -333,8 +328,7 @@ PipId Arch::getPipByName(IdStringList name) const NPNR_ASSERT(dst_index != -1); for (int i = 0; i < tile_info.num_pips; i++) { - if (tile_info.pip_data[i].site == site && - tile_info.pip_data[i].src_index == src_index && + if (tile_info.pip_data[i].site == site && tile_info.pip_data[i].src_index == src_index && tile_info.pip_data[i].dst_index == dst_index) { PipId ret; @@ -358,13 +352,13 @@ PipId Arch::getPipByName(IdStringList name) const for (int i = 0; i < tile_info.num_wires; i++) { if (tile_info.wire_data[i].site == -1 && tile_info.wire_data[i].name == src_wire_name.index) { src_index = i; - if(dst_index != -1) { + if (dst_index != -1) { break; } } if (tile_info.wire_data[i].site == -1 && tile_info.wire_data[i].name == dst_wire_name.index) { dst_index = i; - if(src_index != -1) { + if (src_index != -1) { break; } } @@ -374,8 +368,7 @@ PipId Arch::getPipByName(IdStringList name) const NPNR_ASSERT(dst_index != -1); for (int i = 0; i < tile_info.num_pips; i++) { - if (tile_info.pip_data[i].src_index == src_index && - tile_info.pip_data[i].dst_index == dst_index) { + if (tile_info.pip_data[i].src_index == src_index && tile_info.pip_data[i].dst_index == dst_index) { PipId ret; ret.tile = tile; @@ -405,7 +398,7 @@ IdStringList Arch::getPipName(PipId pip) const auto &site = chip_info->sites[tile.sites[pip_info.site]]; auto &bel = tile_type.bel_data[pip_info.bel]; IdString bel_name(bel.name); - if(bel.category == BEL_CATEGORY_LOGIC) { + if (bel.category == BEL_CATEGORY_LOGIC) { // This is a psuedo pip IdString src_wire_name = IdString(tile_type.wire_data[pip_info.src_index].name); IdString dst_wire_name = IdString(tile_type.wire_data[pip_info.dst_index].name); @@ -413,7 +406,7 @@ IdStringList Arch::getPipName(PipId pip) const std::array ids{id(site.name.get()), pip}; return IdStringList(ids); - } else if(bel.category == BEL_CATEGORY_ROUTING) { + } else if (bel.category == BEL_CATEGORY_ROUTING) { // This is a site pip. IdString pin_name(bel.ports[pip_info.extra_data]); std::array ids{id(site.name.get()), bel_name, pin_name}; @@ -448,7 +441,7 @@ BelId Arch::getBelByLocation(Loc loc) const bi.tile = getTileIndex(loc); auto &li = locInfo(bi); - if(loc.z >= li.num_bels) { + if (loc.z >= li.num_bels) { return BelId(); } else { bi.index = loc.z; @@ -489,10 +482,7 @@ ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const return {x0, y0, x1, y1}; } -delay_t Arch::getWireRipupDelayPenalty(WireId wire) const -{ - return getRipupDelayPenalty(); -} +delay_t Arch::getWireRipupDelayPenalty(WireId wire) const { return getRipupDelayPenalty(); } bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; } @@ -518,10 +508,7 @@ bool Arch::route() // ----------------------------------------------------------------------- -std::vector Arch::getDecalGraphics(DecalId decal) const -{ - return {}; -} +std::vector Arch::getDecalGraphics(DecalId decal) const { return {}; } DecalXY Arch::getBelDecal(BelId bel) const { diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h index 2f2cddfa..285eb3f2 100644 --- a/fpga_interchange/arch.h +++ b/fpga_interchange/arch.h @@ -40,10 +40,7 @@ template struct RelPtr // reinterpret_cast(this); // } - const T *get() const - { - return reinterpret_cast(reinterpret_cast(this) + offset); - } + const T *get() const { return reinterpret_cast(reinterpret_cast(this) + offset); } const T &operator[](size_t index) const { return get()[index]; } @@ -52,7 +49,6 @@ template struct RelPtr const T *operator->() const { return get(); } }; - // Flattened site indexing. // // To enable flat BelId.z spaces, every tile and sites within that tile are @@ -72,9 +68,9 @@ template struct RelPtr // wires (or vise-versa). NPNR_PACKED_STRUCT(struct BelInfoPOD { - int32_t name; // bel name (in site) constid - int32_t type; // Type name constid - int32_t bel_bucket; // BEL bucket constid. + int32_t name; // bel name (in site) constid + int32_t type; // Type name constid + int32_t bel_bucket; // BEL bucket constid. int32_t num_bel_wires; RelPtr ports; // port name constid @@ -89,7 +85,8 @@ NPNR_PACKED_STRUCT(struct BelInfoPOD { RelPtr valid_cells; // Bool array, length of number_cells. }); -enum BELCategory { +enum BELCategory +{ // BEL is a logic element BEL_CATEGORY_LOGIC = 0, // BEL is a site routing mux @@ -231,8 +228,7 @@ struct BelIterator BelIterator operator++() { cursor_index++; - while (cursor_tile < chip->num_tiles && - cursor_index >= tileInfo(chip, cursor_tile).num_bels) { + while (cursor_tile < chip->num_tiles && cursor_index >= tileInfo(chip, cursor_tile).num_bels) { cursor_index = 0; cursor_tile++; } @@ -279,8 +275,8 @@ struct FilteredBelIterator FilteredBelIterator operator++() { ++b; - while(b != e) { - if(filter(*b)) { + while (b != e) { + if (filter(*b)) { break; } @@ -311,19 +307,20 @@ struct FilteredBelIterator struct FilteredBelRange { - FilteredBelRange(BelIterator bel_b, BelIterator bel_e, std::function filter) { + FilteredBelRange(BelIterator bel_b, BelIterator bel_e, std::function filter) + { b.filter = filter; b.b = bel_b; b.e = bel_e; - if(b.b != b.e && !filter(*b.b)) { + if (b.b != b.e && !filter(*b.b)) { ++b; } e.b = bel_e; e.e = bel_e; - if(b != e) { + if (b != e) { NPNR_ASSERT(filter(*b.b)); } } @@ -342,16 +339,10 @@ struct TileWireIterator WireId baseWire; int cursor = -1; - void operator++() { - cursor++; - } + void operator++() { cursor++; } - bool operator==(const TileWireIterator &other) const { - return cursor == other.cursor; - } - bool operator!=(const TileWireIterator &other) const { - return cursor != other.cursor; - } + bool operator==(const TileWireIterator &other) const { return cursor == other.cursor; } + bool operator!=(const TileWireIterator &other) const { return cursor != other.cursor; } // Returns a *denormalised* identifier always pointing to a tile wire rather than a node WireId operator*() const @@ -635,23 +626,13 @@ struct IdStringIterator { const int32_t *cursor; - void operator++() - { - cursor += 1; - } + void operator++() { cursor += 1; } - bool operator!=(const IdStringIterator &other) const { - return cursor != other.cursor; - } + bool operator!=(const IdStringIterator &other) const { return cursor != other.cursor; } - bool operator==(const IdStringIterator &other) const { - return cursor == other.cursor; - } + bool operator==(const IdStringIterator &other) const { return cursor == other.cursor; } - IdString operator*() const - { - return IdString(*cursor); - } + IdString operator*() const { return IdString(*cursor); } }; struct IdStringRange @@ -665,18 +646,11 @@ struct BelBucketIterator { IdStringIterator cursor; - void operator++() - { - ++cursor; - } + void operator++() { ++cursor; } - bool operator!=(const BelBucketIterator &other) const { - return cursor != other.cursor; - } + bool operator!=(const BelBucketIterator &other) const { return cursor != other.cursor; } - bool operator==(const BelBucketIterator &other) const { - return cursor == other.cursor; - } + bool operator==(const BelBucketIterator &other) const { return cursor == other.cursor; } BelBucketId operator*() const { @@ -729,27 +703,28 @@ struct Arch : BaseCtx // ------------------------------------------------- - uint32_t getTileIndex(int x, int y) const { - return (y * chip_info->width + x); - } - uint32_t getTileIndex(Loc loc) const { - return getTileIndex(loc.x, loc.y); - } - template void getTileXY(TileIndex tile_index, CoordIndex *x, CoordIndex *y) const { + uint32_t getTileIndex(int x, int y) const { return (y * chip_info->width + x); } + uint32_t getTileIndex(Loc loc) const { return getTileIndex(loc.x, loc.y); } + template + void getTileXY(TileIndex tile_index, CoordIndex *x, CoordIndex *y) const + { *x = tile_index % chip_info->width; *y = tile_index / chip_info->width; } - template void getTileLoc(TileIndex tile_index, Loc * loc) const { + template void getTileLoc(TileIndex tile_index, Loc *loc) const + { getTileXY(tile_index, &loc->x, &loc->y); } int getGridDimX() const { return chip_info->width; } int getGridDimY() const { return chip_info->height; } - int getTileBelDimZ(int x, int y) const { + int getTileBelDimZ(int x, int y) const + { return chip_info->tile_types[chip_info->tiles[getTileIndex(x, y)].type].num_bels; } - int getTilePipDimZ(int x, int y) const { + int getTilePipDimZ(int x, int y) const + { return chip_info->tile_types[chip_info->tiles[getTileIndex(x, y)].type].number_sites; } char getNameDelimiter() const { return '/'; } @@ -793,10 +768,7 @@ struct Arch : BaseCtx refreshUiBel(bel); } - bool checkBelAvail(BelId bel) const - { - return tileStatus[bel.tile].boundcells[bel.index] == nullptr; - } + bool checkBelAvail(BelId bel) const { return tileStatus[bel.tile].boundcells[bel.index] == nullptr; } CellInfo *getBoundBelCell(BelId bel) const { @@ -841,9 +813,7 @@ struct Arch : BaseCtx return false; } - bool getBelHidden(BelId bel) const { - return locInfo(bel).bel_data[bel.index].category != BEL_CATEGORY_LOGIC; - } + bool getBelHidden(BelId bel) const { return locInfo(bel).bel_data[bel.index].category != BEL_CATEGORY_LOGIC; } IdString getBelType(BelId bel) const { @@ -853,7 +823,8 @@ struct Arch : BaseCtx std::vector> getBelAttrs(BelId bel) const; - int getBelPinIndex(BelId bel, IdString pin) const { + int getBelPinIndex(BelId bel, IdString pin) const + { NPNR_ASSERT(bel != BelId()); int num_bel_wires = locInfo(bel).bel_data[bel.index].num_bel_wires; const int32_t *ports = locInfo(bel).bel_data[bel.index].ports.get(); @@ -878,7 +849,7 @@ struct Arch : BaseCtx IdStringRange str_range; str_range.b.cursor = &ports[0]; - str_range.e.cursor = &ports[num_bel_wires-1]; + str_range.e.cursor = &ports[num_bel_wires - 1]; return str_range; } @@ -909,8 +880,7 @@ struct Arch : BaseCtx std::array ids{id(site.name.get()), IdString(locInfo(wire).wire_data[wire.index].name)}; return IdStringList(ids); } else { - int32_t tile = wire.tile == -1 ? chip_info->nodes[wire.index].tile_wires[0].tile - : wire.tile; + int32_t tile = wire.tile == -1 ? chip_info->nodes[wire.index].tile_wires[0].tile : wire.tile; IdString tile_name = id(chip_info->tiles[tile].name.get()); std::array ids{tile_name, IdString(wireInfo(wire).name)}; return IdStringList(ids); @@ -1092,10 +1062,7 @@ struct Arch : BaseCtx return p2n == pip_to_net.end() ? nullptr : p2n->second; } - WireId getConflictingPipWire(PipId pip) const - { - return getPipDstWire(pip); - } + WireId getConflictingPipWire(PipId pip) const { return getPipDstWire(pip); } NetInfo *getConflictingPipNet(PipId pip) const { @@ -1136,10 +1103,7 @@ struct Arch : BaseCtx return canonicalWireId(chip_info, pip.tile, locInfo(pip).pip_data[pip.index].dst_index); } - DelayInfo getPipDelay(PipId pip) const - { - return DelayInfo(); - } + DelayInfo getPipDelay(PipId pip) const { return DelayInfo(); } DownhillPipRange getPipsDownhill(WireId wire) const { @@ -1229,36 +1193,38 @@ struct Arch : BaseCtx // ------------------------------------------------- - const BelBucketRange getBelBuckets() const { + const BelBucketRange getBelBuckets() const + { BelBucketRange bel_bucket_range; bel_bucket_range.b.cursor.cursor = &chip_info->bel_buckets[0]; - bel_bucket_range.e.cursor.cursor = &chip_info->bel_buckets[chip_info->number_bel_buckets-1]; + bel_bucket_range.e.cursor.cursor = &chip_info->bel_buckets[chip_info->number_bel_buckets - 1]; return bel_bucket_range; } - BelBucketId getBelBucketForBel(BelId bel) const { + BelBucketId getBelBucketForBel(BelId bel) const + { BelBucketId bel_bucket; bel_bucket.name = IdString(locInfo(bel).bel_data[bel.index].bel_bucket); return bel_bucket; } - const IdStringRange getCellTypes() const { - const CellMapPOD & cell_map = *chip_info->cell_map; + const IdStringRange getCellTypes() const + { + const CellMapPOD &cell_map = *chip_info->cell_map; IdStringRange id_range; id_range.b.cursor = &cell_map.cell_names[0]; - id_range.e.cursor = &cell_map.cell_names[cell_map.number_cells-1]; + id_range.e.cursor = &cell_map.cell_names[cell_map.number_cells - 1]; return id_range; } - IdString getBelBucketName(BelBucketId bucket) const { - return bucket.name; - } + IdString getBelBucketName(BelBucketId bucket) const { return bucket.name; } - BelBucketId getBelBucketByName(IdString name) const { - for(BelBucketId bel_bucket : getBelBuckets()) { - if(bel_bucket.name == name) { + BelBucketId getBelBucketByName(IdString name) const + { + for (BelBucketId bel_bucket : getBelBuckets()) { + if (bel_bucket.name == name) { return bel_bucket; } } @@ -1267,39 +1233,42 @@ struct Arch : BaseCtx return BelBucketId(); } - size_t getCellTypeIndex(IdString cell_type) const { - const CellMapPOD & cell_map = *chip_info->cell_map; + size_t getCellTypeIndex(IdString cell_type) const + { + const CellMapPOD &cell_map = *chip_info->cell_map; int cell_offset = cell_type.index - cell_map.cell_names[0]; NPNR_ASSERT(cell_type.index >= 0 && cell_type.index < cell_map.number_cells); return cell_offset; } - BelBucketId getBelBucketForCellType(IdString cell_type) const { + BelBucketId getBelBucketForCellType(IdString cell_type) const + { BelBucketId bucket; - const CellMapPOD & cell_map = *chip_info->cell_map; + const CellMapPOD &cell_map = *chip_info->cell_map; bucket.name = cell_map.cell_bel_buckets[getCellTypeIndex(cell_type)]; return bucket; } - FilteredBelRange getBelsInBucket(BelBucketId bucket) const { + FilteredBelRange getBelsInBucket(BelBucketId bucket) const + { BelRange range = getBels(); - FilteredBelRange filtered_range( - range.begin(), range.end(), [this, bucket](BelId bel) { - return getBelBucketForBel(bel) == bucket; - }); + FilteredBelRange filtered_range(range.begin(), range.end(), + [this, bucket](BelId bel) { return getBelBucketForBel(bel) == bucket; }); return filtered_range; } - bool isValidBelForCellType(IdString cell_type, BelId bel) const { + bool isValidBelForCellType(IdString cell_type, BelId bel) const + { return locInfo(bel).bel_data[bel.index].valid_cells[getCellTypeIndex(cell_type)]; } // Whether or not a given cell can be placed at a given Bel // This is not intended for Bel type checks, but finer-grained constraints // such as conflicting set/reset signals, etc - bool isValidBelForCell(CellInfo *cell, BelId bel) const { + bool isValidBelForCell(CellInfo *cell, BelId bel) const + { NPNR_ASSERT(isValidBelForCellType(cell->type, bel)); // FIXME: Implement this @@ -1307,7 +1276,8 @@ struct Arch : BaseCtx } // Return true whether all Bels at a given location are valid - bool isBelLocationValid(BelId bel) const { + bool isBelLocationValid(BelId bel) const + { // FIXME: Implement this return true; } @@ -1332,8 +1302,7 @@ struct Arch : BaseCtx return chip_info->tile_types[chip_info->tiles[id.tile].type]; } - void writePhysicalNetlist(const std::string &filename) const { - } + void writePhysicalNetlist(const std::string &filename) const {} }; NEXTPNR_NAMESPACE_END diff --git a/fpga_interchange/archdefs.h b/fpga_interchange/archdefs.h index 66d72f1c..b3571fab 100644 --- a/fpga_interchange/archdefs.h +++ b/fpga_interchange/archdefs.h @@ -123,15 +123,13 @@ struct DecalId bool operator!=(const DecalId &other) const { return false; } }; -struct BelBucketId { +struct BelBucketId +{ IdString name; bool operator==(const BelBucketId &other) const { return (name == other.name); } bool operator!=(const BelBucketId &other) const { return (name != other.name); } - bool operator<(const BelBucketId &other) const - { - return name < other.name; - } + bool operator<(const BelBucketId &other) const { return name < other.name; } }; struct ArchNetInfo diff --git a/fpga_interchange/main.cc b/fpga_interchange/main.cc index a2eab572..644bf8c0 100644 --- a/fpga_interchange/main.cc +++ b/fpga_interchange/main.cc @@ -72,9 +72,7 @@ std::unique_ptr FpgaInterchangeCommandHandler::createContext(std::unord return std::unique_ptr(new Context(chipArgs)); } -void FpgaInterchangeCommandHandler::customAfterLoad(Context *ctx) -{ -} +void FpgaInterchangeCommandHandler::customAfterLoad(Context *ctx) {} int main(int argc, char *argv[]) { -- cgit v1.2.3