From 0a8c411692629b4748673b11f8dca8c3db7552fb Mon Sep 17 00:00:00 2001 From: gatecat Date: Wed, 14 Sep 2022 09:24:49 +0200 Subject: ice40: Fix UltraPlus BRAM clock polarity Signed-off-by: gatecat --- ice40/bitstream.cc | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 3e50c065..2e1a6d4e 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -620,9 +620,13 @@ void write_asc(const Context *ctx, std::ostream &out) bool negclk_w = get_param_or_def(ctx, cell.second.get(), id_NEG_CLK_W); int write_mode = get_param_or_def(ctx, cell.second.get(), id_WRITE_MODE); int read_mode = get_param_or_def(ctx, cell.second.get(), id_READ_MODE); - set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w); - set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r); - + if (ctx->args.type == ArchArgs::UP5K || ctx->args.type == ArchArgs::UP3K) { + set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_r); + set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_w); + } else { + set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w); + set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r); + } set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_0", write_mode & 0x1); set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_1", write_mode & 0x2); set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_2", read_mode & 0x1); -- cgit v1.2.3