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* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-191-1/+1
| | | | | | | | | | | | This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: router1 speedup based on #867gatecat2021-12-171-2/+70
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Add resource cost overridesgatecat2021-09-241-0/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: LUT permutation supportgatecat2021-09-241-0/+31
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #823 from YosysHQ/gatecat/nexus-r1-tweaksgatecat2021-09-221-1/+1
|\ | | | | nexus: Tweaks for router1 performance
| * nexus: Tweaks for router1 performancegatecat2021-09-221-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | nexus: Fix DSP macro placementgatecat2021-09-221-0/+4
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Fix getBelGlobalBufgatecat2021-09-021-1/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Add IOLOGIC pins datagatecat2021-07-281-2/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Disable center DCC-thrus on 17k devicegatecat2021-06-161-0/+16
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fixing old emails and names in copyrightsgatecat2021-06-121-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Using hashlib in archesgatecat2021-06-021-6/+6
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* router2: Add heatmap by routing resource typegatecat2021-05-201-0/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-151-6/+9
| | | | | | | | | | | | | | | | | | | "nextpnr.h" is no longer the god header. Important improvements: - Functions in log.h can be used without including BaseCtx/Arch/Context. This means that log_X functions can be called without included "nextpnr.h" - NPNR_ASSERT can be used without including "nextpnr.h" by including "nextpnr_assertions.h". This allows NPNR_ASSERT to be used safely in any header file. - Types defined in "archdefs.h" are now available without including BaseCtx/Arch/Context. This means that utility classes that will be used inside of BaseCtx/Arch/Context can be defined safely in a self-contained header. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* nexus: Add pin definitions for DPHYgatecat2021-03-081-0/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Fix global handling for LIFCL-17gatecat2021-03-031-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Fix getPipDelay returning negative after refactorgatecat2021-02-231-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-26/+11
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* Remove isValidBelForCellgatecat2021-02-161-5/+0
| | | | | | | | | | | | | | | | | This Arch API dates from when we were first working out how to implement placement validity checking, and in practice is little used by the core parts of placer1/HeAP and the Arch implementation involves a lot of duplication with isBelLocationValid. In the short term; placement validity checking is better served by the combination of checkBelAvail and isValidBelForCellType before placement; followed by isBelLocationValid after placement (potentially after moving/swapping multiple cells). Longer term, removing this API makes things a bit cleaner for a new validity checking API. Signed-off-by: gatecat <gatecat@ds0.me>
* Add getBelHidden and add some missing "override" statements.Keith Rothman2021-02-111-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add BaseArchRanges for default ArchRanges typesgatecat2021-02-091-16/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #568 from YosysHQ/dave/arch-overridegatecat2021-02-081-257/+102
|\ | | | | Create a new BaseArch that formally specifies the Arch API and provides some base implementations
| * Use 'T' postfix to disambiguate LHS and RHS of usingD. Shah2021-02-081-21/+21
| | | | | | | | | | | | | | Arches might otherwise have range types named ambigiously with the entry in ArchRanges. Signed-off-by: D. Shah <dave@ds0.me>
| * Add archArgs and archArgsToId to Arch APID. Shah2021-02-051-2/+3
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
| * nexus: Switch to BaseArchD. Shah2021-02-051-255/+99
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
* | Use RelSlice::ssize instead of cast-to-int throughoutD. Shah2021-02-081-10/+10
|/ | | | Signed-off-by: D. Shah <dave@ds0.me>
* Mark IdString and IdStringList single argument constructors explicit.Keith Rothman2021-02-041-2/+2
| | | | | | | | | Single argument constructors will silently convert to that type. This is typically not the right thing to do. For example, the nexus and ice40 arch_pybindings.h files were incorrectly parsing bel name strings, etc. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* nexus: Implement IdStringList for all arch object namesD. Shah2021-02-021-22/+21
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* arch: Add getNameDelimiter API for string listsD. Shah2021-02-021-0/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Run "make clangformat".Keith Rothman2021-02-021-18/+14
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Rename Partition -> BelBucket.Keith Rothman2021-02-021-19/+19
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add Partition APIs to ice40, nexus, gowin archs.Keith Rothman2021-02-021-0/+43
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial refactoring of placer API.Keith Rothman2021-02-021-0/+5
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Seperate PipRange types in pybindings_shared.Keith Rothman2021-02-011-1/+0
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* cleanup: Spelling fixesD. Shah2021-01-281-1/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Move RelPtr/RelSlice out of arches into commonD. Shah2021-01-271-39/+1
| | | | | | | The bba approach seems widely used enough that it's reasonable for this to become part of common code. Signed-off-by: D. Shah <dave@ds0.me>
* nexus: Switch from RelPtr to RelSliceD. Shah2021-01-271-85/+77
| | | | | | | | | | This replaces RelPtrs and a separate length field with a Rust-style slice containing both a pointer and a length; with bounds checking always enforced. Thus iterating over these structures is both cleaner and safer. Signed-off-by: D. Shah <dave@ds0.me>
* nexus: Fix LRAM pin typesDavid Shah2020-12-071-8/+9
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Add support for initialised LRAMDavid Shah2020-12-071-3/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Add basic LRAM support (no init)David Shah2020-12-021-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Fix db integrity checkDavid Shah2020-11-301-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Add post-place LUTFF optimisationDavid Shah2020-11-301-13/+10
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Preliminary integration of DSP timing dataDavid Shah2020-11-301-0/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Fix slow routing around DSPsDavid Shah2020-11-301-0/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Fix validity checking when DSPs are usedDavid Shah2020-11-301-2/+9
| | | | Signed-off-by: David Shah <dave@ds0.me>
* timing: Add a few more cell typesDavid Shah2020-11-301-0/+9
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Swap sort order to make some lookups easierDavid Shah2020-11-301-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Add cell delay lookupDavid Shah2020-11-301-0/+6
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Lookup speed grade and pip delaysDavid Shah2020-11-301-1/+10
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Add timing structures to BBADavid Shah2020-11-301-1/+49
| | | | Signed-off-by: David Shah <dave@ds0.me>
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