iCE40/nextpnr - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	machxo2: Python bindings and stub GUI	gatecat	2021-02-12	5	-6/+188
\| \| \| \|	Signed-off-by: gatecat <gatecat@ds0.me>
*	machxo2: Use snake_case for non-ArchAPI functions	gatecat	2021-02-12	4	-63/+63
\| \| \| \|	Signed-off-by: gatecat <gatecat@ds0.me>
*	machxo2: Use IdStringLists in earnest	gatecat	2021-02-12	2	-76/+70
\| \| \| \|	Signed-off-by: gatecat <gatecat@ds0.me>
*	machxo2: Update with Arch API changes	gatecat	2021-02-12	7	-464/+115
\| \| \| \|	Signed-off-by: gatecat <gatecat@ds0.me>
*	machxo2: Prepare README.md for first PR.	William D. Jones	2021-02-12	1	-4/+36
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*	machxo2: Add prefix parameter to simtest.sh. Remove show command from	William D. Jones	2021-02-12	3	-40/+43
\| \| \| \|	simtest.sh. Update README.md.
*	machxo2: Add prefix parameter to simple.sh. Update README.md.	William D. Jones	2021-02-12	2	-14/+14
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*	machxo2: Fill in more about mitertest.sh in README.md and clean up a bit.	William D. Jones	2021-02-12	1	-4/+27
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*	machxo2: Add two new examples: blinky_ext and aforementioned UART.	William D. Jones	2021-02-12	3	-0/+238
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*	machxo2: auto-top does not work for smt miter either.	William D. Jones	2021-02-12	1	-1/+1
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*	machxo2: Fix unhelpful comment in mitertest.sh.	William D. Jones	2021-02-12	1	-1/+0
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*	machxo2: Verilog examples using OSCH cannot be simulated in mitertest.sh. ↵	William D. Jones	2021-02-12	1	-3/+7
\| \| \| \|	Remove show from mitertest.sh.
*	machxo2: Add prefix parameter to mitertest.sh. All Verilog files top modules ↵	William D. Jones	2021-02-12	3	-37/+37
\| \| \| \|	named "top".
*	machxo2: Add prefix paramter to demo.sh.	William D. Jones	2021-02-12	4	-22/+37
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*	Add demo with RGB LED	mtnrbq	2021-02-12	2	-0/+43
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*	machxo2: Fix packing when FF is driven by a constant; UART test core working ↵	William D. Jones	2021-02-12	2	-1/+3
\| \| \| \|	on silicon, fails post-synth sim.
*	machxo2: Add packing logic to handle FFs fed with constant value; UART test ↵	William D. Jones	2021-02-12	3	-5/+39
\| \| \| \|	core routes.
*	machxo2: Add additional packing phase to pack remaining FFs.	William D. Jones	2021-02-12	1	-0/+38
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*	machxo2: Don't write out config bits for cells without location info.	William D. Jones	2021-02-12	1	-1/+2
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*	machxo2: Special-case left and right I/O wire names in ASCII generation.	William D. Jones	2021-02-12	1	-1/+35
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*	machxo2: Add quickstart README.md.	William D. Jones	2021-02-12	1	-0/+73
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*	machxo2: Fail CMake configuration is BUILD_PYTHON is ON (not supported for now).	William D. Jones	2021-02-12	1	-0/+3
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*	machxo2: Fix REGMODE identifier (per slice, not per-FF).	William D. Jones	2021-02-12	2	-5/+2
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*	machxo2: Add demo.sh TinyFPGA Ax example.	William D. Jones	2021-02-12	4	-1/+50
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*	machxo2: clang format.	William D. Jones	2021-02-12	4	-29/+34
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*	machxo2: Fix reversed interpretation of REG_SD config bits.	William D. Jones	2021-02-12	1	-6/+0
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*	machxo2: Add bitstream generation for OSCH.	William D. Jones	2021-02-12	1	-0/+4
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*	machxo2: Add basic bitstream generation for PIC tiles and I/O.	William D. Jones	2021-02-12	1	-0/+26
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*	machxo2: Add REGMODE to bitstream output.	William D. Jones	2021-02-12	1	-0/+1
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*	machxo2: Checkpoint commit for slice bitstream generation.	William D. Jones	2021-02-12	3	-1/+121
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*	machxo2: Write out pips to bitstream.	William D. Jones	2021-02-12	3	-0/+83
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*	machxo2: Emit empty bitstream file.	William D. Jones	2021-02-12	1	-0/+37
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*	machxo2: Add/fix copyright banners.	William D. Jones	2021-02-12	8	-5/+12
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*	machxo2: Add stub bitstream writer plus support files.	William D. Jones	2021-02-12	5	-2/+559
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*	machxo2: Tweak A-star parameters for acceptable performance.	William D. Jones	2021-02-12	2	-3/+26
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*	machxo2: Fix getWireName.	William D. Jones	2021-02-12	1	-1/+1
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*	machxo2: Fix typos where absolute positions were treated as relative.	William D. Jones	2021-02-12	1	-6/+6
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*	machxo2: Finish implementing Wire API functions. nextpnr segfaults on ↵	William D. Jones	2021-02-12	2	-12/+43
\| \| \| \|	example with constraints.
*	machxo2: Finish implementing Pip API functions.	William D. Jones	2021-02-12	2	-27/+67
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*	machxo2: Implement 4 more Wire/Pip API functions.	William D. Jones	2021-02-12	2	-32/+94
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*	machxo2: Add stub getAttrs API functions.	William D. Jones	2021-02-12	2	-13/+21
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*	machxo2: Implement getByName/getName for Wires and Pips.	William D. Jones	2021-02-12	2	-13/+94
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*	machxo2: Convert facade_import to use pybind API from pytrellis.	William D. Jones	2021-02-12	1	-9/+7
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*	machxo2: Use attrmvcp in yosys to implement LOC constraint and only check ↵	William D. Jones	2021-02-12	1	-37/+22
\| \| \| \|	for LOC on FACADE_IO.
*	machxo2: Detect LOC attributes during packing to implement rudimentary user ↵	William D. Jones	2021-02-12	3	-0/+61
\| \| \| \|	constraints.
*	machxo2: clang format.	William D. Jones	2021-02-12	5	-74/+32
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*	machxo2: Import remaining iterators from ECP5.	William D. Jones	2021-02-12	1	-0/+154
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*	machxo2: Implement WireId/PipId, complete Bel part of API.	William D. Jones	2021-02-12	3	-2/+72
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*	machxo2: Implement all of Bel API except getBelPinWire.	William D. Jones	2021-02-12	2	-12/+79
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*	machxo2: Fix place phase segfault. Placement suceeds with warning of no clock.	William D. Jones	2021-02-12	1	-0/+2
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