| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | * | | | timing: Model clock to Q times | David Shah | 2018-07-24 | 1 | -0/+15 | |
| | * | | | ice40: Trim BRAM constant inputs, reduces routing congestion around BRAM | David Shah | 2018-07-24 | 1 | -0/+3 | |
| | * | | | ice40: Fix SPRAM and other primitives in corners other than (0, 0) | David Shah | 2018-07-24 | 1 | -1/+1 | |
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| * | | | ice40: fixes before review | Sergiusz Bazanski | 2018-07-24 | 5 | -45/+13 | |
| * | | | ice40: move PLL->IO from pseudo pip to second uphill bel | Sergiusz Bazanski | 2018-07-24 | 3 | -69/+40 | |
| * | | | ice40: emit list of upbels in chipdb | Sergiusz Bazanski | 2018-07-24 | 4 | -16/+22 | |
| * | | | clang-format | Sergiusz Bazanski | 2018-07-24 | 3 | -66/+74 | |
| * | | | ice40: A slightly nicer way to do this. | Sergiusz Bazanski | 2018-07-24 | 1 | -46/+31 | |
| * | | | ice40: Move spliceLUT back to pack.cc | Sergiusz Bazanski | 2018-07-24 | 3 | -56/+53 | |
| * | | | ice40: Prevent placement of SB_IOs in IO blocks used by PLL outputs | Sergiusz Bazanski | 2018-07-24 | 1 | -0/+24 | |
| * | | | ice40: Refactor PLL/LOCK LUT splicing out into Arch:: | Sergiusz Bazanski | 2018-07-24 | 4 | -74/+59 | |
| * | | | ice40: Emit feed-through LUTs for PLL/LOCK | Sergiusz Bazanski | 2018-07-24 | 2 | -2/+159 | |
| * | | | ice40: Fail early on SB_PLL40_*_PAD cells | Sergiusz Bazanski | 2018-07-24 | 2 | -0/+14 | |
| * | | | ice40: Implement emitting PLLs | Sergiusz Bazanski | 2018-07-24 | 9 | -16/+269 | |
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| * | | Add Context::archcheck() and "nextpnr-ice40 --test" | Clifford Wolf | 2018-07-23 | 2 | -40/+60 | |
| * | | Remove getBelsByType() API | Clifford Wolf | 2018-07-23 | 1 | -14/+0 | |
| * | | clangformat | David Shah | 2018-07-23 | 1 | -2/+3 | |
| * | | Add getGridDimX(), getGridDimY(), getTileDimZ() API | Clifford Wolf | 2018-07-23 | 1 | -0/+6 | |
| * | | Bugfix in iCE40 chipdb.py | Clifford Wolf | 2018-07-23 | 1 | -3/+0 | |
| * | | Move to new API and remove deprecated | Miodrag Milanovic | 2018-07-22 | 3 | -63/+40 | |
| * | | Add Arch::getBelPins() to generic and iCE40 archs | Clifford Wolf | 2018-07-22 | 2 | -0/+17 | |
| * | | Add Arch::getBelPinType() and Arch::getWireBelPins() in iCE40 arch | Clifford Wolf | 2018-07-22 | 3 | -4/+57 | |
| * | | Rename getWireBelPin to getBelPinWire | Clifford Wolf | 2018-07-22 | 6 | -18/+18 | |
| * | | clangformat | Clifford Wolf | 2018-07-22 | 3 | -8/+4 | |
| * | | Merge branch 'q3k/lock-2-electric-boogaloo' into 'master' | Clifford Wolf | 2018-07-21 | 2 | -4/+12 | |
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| | * | | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/lock-2-elec... | Sergiusz Bazanski | 2018-07-21 | 9 | -543/+904 | |
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| | * | | Re-enable drawing Pips. | Sergiusz Bazanski | 2018-07-20 | 1 | -3/+3 | |
| | * | | clang-format | Sergiusz Bazanski | 2018-07-20 | 1 | -1/+1 | |
| | * | | Nuke IdStringDB | Sergiusz Bazanski | 2018-07-20 | 1 | -1/+1 | |
| | * | | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/lock-2-elec... | Sergiusz Bazanski | 2018-07-20 | 16 | -95/+361 | |
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| | * | | | WIP. | Serge Bazanski | 2018-07-17 | 1 | -0/+8 | |
| | * | | | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/lock-2-elec... | Serge Bazanski | 2018-07-17 | 1 | -4/+4 | |
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| | * \ \ \ | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/lock-2-elec... | Serge Bazanski | 2018-07-15 | 5 | -14/+261 | |
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| | * | | | | | Refactor IdString functionality into IdStringDB | Serge Bazanski | 2018-07-14 | 1 | -1/+1 | |
| * | | | | | | Add Loc constructors | Clifford Wolf | 2018-07-21 | 1 | -6/+1 | |
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| * | | | | | Added driver and users for nets | Miodrag Milanovic | 2018-07-21 | 1 | -0/+8 | |
| * | | | | | Merge branch 'router1ng' into 'master' | Clifford Wolf | 2018-07-21 | 1 | -0/+1 | |
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| | * | | | | | Refactoring of router1 | Clifford Wolf | 2018-07-21 | 1 | -0/+1 | |
| * | | | | | | Map ports to nets | Miodrag Milanovic | 2018-07-21 | 1 | -0/+14 | |
| * | | | | | | create io cells out of asc | Miodrag Milanovic | 2018-07-21 | 1 | -0/+27 | |
| * | | | | | | add cells that are in default state or no configuration | Miodrag Milanovic | 2018-07-21 | 1 | -0/+40 | |
| * | | | | | | Add used cells and attach them to bels | Miodrag Milanovic | 2018-07-21 | 1 | -0/+39 | |
| * | | | | | | Assign proper pips | Miodrag Milanovic | 2018-07-21 | 1 | -9/+27 | |
| * | | | | | | add only missing net | Miodrag Milanovic | 2018-07-21 | 1 | -3/+6 | |
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| * | | | | | Change DelayInfo semantics to what we actually need | Clifford Wolf | 2018-07-21 | 1 | -3/+8 | |
| * | | | | | Add getWireDelay API | Clifford Wolf | 2018-07-21 | 1 | -0/+6 | |
| * | | | | | Fix warnings and status | Miodrag Milanovic | 2018-07-21 | 2 | -2/+19 | |
| * | | | | | Made save project work as well | Miodrag Milanovic | 2018-07-21 | 1 | -3/+0 | |
| * | | | | | fix introduced bug | Miodrag Milanovic | 2018-07-21 | 1 | -0/+2 | |
| * | | | | | Bind wires to net | Miodrag Milanovic | 2018-07-20 | 1 | -629/+637 | |
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index : iCE40/nextpnr | |
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