Commit message (Collapse) | Author | Age | Files | Lines | |
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* | ice40: PLLs can't conflict with themselves | David Shah | 2019-02-09 | 1 | -0/+2 |
| | | | | | | Fixes error building testcase from #145 Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40: Don't create PLLOUT_B buffer for single-output PLL variants | David Shah | 2019-02-09 | 1 | -1/+6 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Merge pull request #211 from smunaut/ice40_ram_attrs | David Shah | 2019-01-21 | 1 | -0/+4 |
|\ | | | | | ice40/pack: Copy attributes to packed cell | ||||
| * | ice40/pack: Copy attributes to packed RAM cells | Sylvain Munaut | 2019-01-19 | 1 | -0/+4 |
| | | | | | | | | | | | | | | Useful to allow manual placement of SPRAM/EBR using BEL attribute for instance Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | | ice40: Add error message if a selected site is not Global Buffer capable | Sylvain Munaut | 2019-01-18 | 1 | -0/+4 |
|/ | | | | | | ... rather than assert()-out during the call to getWireBelPins() call Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Improve handling of unconstrained IO | David Shah | 2018-12-26 | 1 | -3/+0 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40: Fix LOCK feedthrough insertion with carry or >8 LUTs | David Shah | 2018-12-20 | 1 | -4/+10 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | ice40: Report error for unsupported PLL FEEDBACK_PATH values | David Shah | 2018-12-06 | 1 | -7/+11 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40: add reset global promotion threshold. | whitequark | 2018-12-04 | 1 | -1/+3 |
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* | ice40: Add support for placing SB_LEDDA_IP block. | Daniel Serpell | 2018-12-01 | 1 | -0/+4 |
| | | | | Signed-off-by: Daniel Serpell <daniel.serpell@gmail.com> | ||||
* | ice40: Add a warning for unconstrained IO | David Shah | 2018-11-29 | 1 | -6/+5 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Merge pull request #157 from whitequark/fanout-thresh | David Shah | 2018-11-29 | 1 | -1/+1 |
|\ | | | | | ice40: raise CE global promotion threshold | ||||
| * | ice40: raise CE global promotion threshold. | whitequark | 2018-11-29 | 1 | -1/+1 |
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* | | ice40: print fanout of nets promoted to globals. | whitequark | 2018-11-28 | 1 | -7/+11 |
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* | ice40: Try to be helpful and suggest using PAD PLL instead of CORE | Sylvain Munaut | 2018-11-28 | 1 | -2/+14 |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Revamp the whole PLL placement/validity check logic | Sylvain Munaut | 2018-11-28 | 1 | -72/+200 |
| | | | | | | | | | | | | | | | | | We do a pre-pass on all the PLLs to place them before packing. To place them: - First pass with all the PADs PLLs since those can only fit at one specific BEL depending on the input connection - Second pass with all the dual outputs CORE PLLs. Those can go anywhere where there is no conflicts with their A & B outputs and used IO pins - Third pass with the single output CORE PLLs. Those have the least constrains. During theses passes, we also check the validity of all their connections. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Finer-grained control of global promotion | David Shah | 2018-11-27 | 1 | -2/+4 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40: During global promotion, only promote if this will actually fit ! | Sylvain Munaut | 2018-11-26 | 1 | -6/+32 |
| | | | | | | | | We need to take into account the global networks that are already used and possibly locked to know what we can promote since all networks can't drive resets / clock-enables Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Fix disconnection of PACKAGEPIN for PAD PLLs | David Shah | 2018-11-24 | 1 | -0/+2 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40/pll: Fix typo when testing for global port output net | Sylvain Munaut | 2018-11-20 | 1 | -1/+1 |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Add support for SB_RGBA_DRV | Sylvain Munaut | 2018-11-19 | 1 | -2/+33 |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Add global network output support for LFOSC/HFOSC | Sylvain Munaut | 2018-11-19 | 1 | -2/+10 |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40/pack: Add helper to constain cells that are unique in the FPGA | Sylvain Munaut | 2018-11-19 | 1 | -0/+16 |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Add support for SB_GB_IO | Sylvain Munaut | 2018-11-19 | 1 | -8/+25 |
| | | | | | | | | | | During packing we replace them by standard SB_IO cells and create the 'fake' SB_GB that matches that IO site global buffer connection. It's done in a separate pass because we need to make sure the nextpnr iob have been dealt first so we have our final Bel location on the SB_IO. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Add support for PLL global outputs via PADIN | Sylvain Munaut | 2018-11-19 | 1 | -40/+23 |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Introduce the concept of forPadIn SB_GB | Sylvain Munaut | 2018-11-19 | 1 | -1/+28 |
| | | | | | | | | | | | | | | Those are cells that are created mainly to handle the various sources a global network can be driven from other than a user net. When the flag is set, this means the global network usually driven by this BEL is in fact driven by something else and so that SB_GB BEL and matching global network can't be used. This is also what gets used to set the extra bits during bitstream generation. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40/pll: Add proper support for PLLOUT_SELECT_xxx attributes | Sylvain Munaut | 2018-11-19 | 1 | -0/+18 |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Minor fix in predicate checking for logic port | Sylvain Munaut | 2018-11-19 | 1 | -2/+3 |
| | | | | | | | - is_sb_pll40 covers all the PLL types - Use helper to test for gbuf Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40/pack: Stop looking for BEL when we have one during PLL placement | Sylvain Munaut | 2018-11-19 | 1 | -0/+1 |
| | | | | | | | Ideally we should first process all the PLL that are constrained somehow (either explicitely or because they are PAD) and then free place the rest. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40/pack: Allow PLL to be constrained via 'BEL' attributes | Sylvain Munaut | 2018-11-19 | 1 | -0/+10 |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40/pack: Make sure we don't use a LOCKED bel when placing PLL | Sylvain Munaut | 2018-11-19 | 1 | -0/+2 |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Add warning if an instanciated SB_IO has its PACKAGE_PIN used elsewhere | Sylvain Munaut | 2018-11-16 | 1 | -0/+5 |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | timing: Add support for clock constraints | David Shah | 2018-11-12 | 1 | -0/+8 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | timing: iCE40 Arch API changes for clocking info | David Shah | 2018-11-12 | 1 | -1/+2 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Add info message for promoted global nets | Clifford Wolf | 2018-10-03 | 1 | -0/+2 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | ice40: Add error for bad PACKAGE_PIN connections | David Shah | 2018-10-03 | 1 | -2/+13 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | clangformat | David Shah | 2018-09-30 | 1 | -15/+23 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | Merge pull request #79 from YosysHQ/ice40lvds | Clifford Wolf | 2018-09-25 | 1 | -1/+1 |
|\ | | | | | ice40: Adding LVDS input support | ||||
| * | ice40: Tristate IO support fixes | David Shah | 2018-09-24 | 1 | -1/+1 |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | | Merge pull request #76 from YosysHQ/plloutglobal_fix | Clifford Wolf | 2018-09-25 | 1 | -2/+36 |
|\ \ | | | | | | | Add needed PLLOUTGLOBAL ports and mapped it | ||||
| * | | Added required checks for PLL and fixed messages eol | Miodrag Milanovic | 2018-09-19 | 1 | -3/+31 |
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| * | | Add needed PLLOUTGLOBAL ports and mapped it properly | Miodrag Milanovic | 2018-09-12 | 1 | -0/+6 |
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* / | ice40: Fix carry packer bug | David Shah | 2018-09-25 | 1 | -2/+2 |
|/ | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | ice40: make PLL packing more robust | Sergiusz Bazanski | 2018-08-19 | 1 | -11/+26 |
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* | Get rid of PortPin and BelType (ice40, generic, docs) | Clifford Wolf | 2018-08-08 | 1 | -3/+3 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Fixing constraint placement bugs | David Shah | 2018-08-03 | 1 | -2/+3 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | Reworking packer and placer to use new generic rel legaliser | David Shah | 2018-08-03 | 1 | -0/+3 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | ice40: Promote 'logic' globals as well as clock/enable/reset | David Shah | 2018-08-03 | 1 | -10/+40 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | ice40: Add HFOSC support, force fabric routing on oscillators for now | David Shah | 2018-08-01 | 1 | -1/+14 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | clangformat | Sergiusz Bazanski | 2018-08-01 | 1 | -6/+6 |
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