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* ice40: Don't constrain to a PLL bel that has already been usedDavid Shah2019-04-011-0/+2
* ice40: Add support for SB_I2C and SB_SPISylvain Munaut2019-03-251-1/+18
* ice40: PLLs can't conflict with themselvesDavid Shah2019-02-091-0/+2
* ice40: Don't create PLLOUT_B buffer for single-output PLL variantsDavid Shah2019-02-091-1/+6
* Merge pull request #211 from smunaut/ice40_ram_attrsDavid Shah2019-01-211-0/+4
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| * ice40/pack: Copy attributes to packed RAM cellsSylvain Munaut2019-01-191-0/+4
* | ice40: Add error message if a selected site is not Global Buffer capableSylvain Munaut2019-01-181-0/+4
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* ice40: Improve handling of unconstrained IODavid Shah2018-12-261-3/+0
* ice40: Fix LOCK feedthrough insertion with carry or >8 LUTsDavid Shah2018-12-201-4/+10
* ice40: Report error for unsupported PLL FEEDBACK_PATH valuesDavid Shah2018-12-061-7/+11
* ice40: add reset global promotion threshold.whitequark2018-12-041-1/+3
* ice40: Add support for placing SB_LEDDA_IP block.Daniel Serpell2018-12-011-0/+4
* ice40: Add a warning for unconstrained IODavid Shah2018-11-291-6/+5
* Merge pull request #157 from whitequark/fanout-threshDavid Shah2018-11-291-1/+1
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| * ice40: raise CE global promotion threshold.whitequark2018-11-291-1/+1
* | ice40: print fanout of nets promoted to globals.whitequark2018-11-281-7/+11
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* ice40: Try to be helpful and suggest using PAD PLL instead of CORESylvain Munaut2018-11-281-2/+14
* ice40: Revamp the whole PLL placement/validity check logicSylvain Munaut2018-11-281-72/+200
* ice40: Finer-grained control of global promotionDavid Shah2018-11-271-2/+4
* ice40: During global promotion, only promote if this will actually fit !Sylvain Munaut2018-11-261-6/+32
* ice40: Fix disconnection of PACKAGEPIN for PAD PLLsDavid Shah2018-11-241-0/+2
* ice40/pll: Fix typo when testing for global port output netSylvain Munaut2018-11-201-1/+1
* ice40: Add support for SB_RGBA_DRVSylvain Munaut2018-11-191-2/+33
* ice40: Add global network output support for LFOSC/HFOSCSylvain Munaut2018-11-191-2/+10
* ice40/pack: Add helper to constain cells that are unique in the FPGASylvain Munaut2018-11-191-0/+16
* ice40: Add support for SB_GB_IOSylvain Munaut2018-11-191-8/+25
* ice40: Add support for PLL global outputs via PADINSylvain Munaut2018-11-191-40/+23
* ice40: Introduce the concept of forPadIn SB_GBSylvain Munaut2018-11-191-1/+28
* ice40/pll: Add proper support for PLLOUT_SELECT_xxx attributesSylvain Munaut2018-11-191-0/+18
* ice40: Minor fix in predicate checking for logic portSylvain Munaut2018-11-191-2/+3
* ice40/pack: Stop looking for BEL when we have one during PLL placementSylvain Munaut2018-11-191-0/+1
* ice40/pack: Allow PLL to be constrained via 'BEL' attributesSylvain Munaut2018-11-191-0/+10
* ice40/pack: Make sure we don't use a LOCKED bel when placing PLLSylvain Munaut2018-11-191-0/+2
* ice40: Add warning if an instanciated SB_IO has its PACKAGE_PIN used elsewhereSylvain Munaut2018-11-161-0/+5
* timing: Add support for clock constraintsDavid Shah2018-11-121-0/+8
* timing: iCE40 Arch API changes for clocking infoDavid Shah2018-11-121-1/+2
* Add info message for promoted global netsClifford Wolf2018-10-031-0/+2
* ice40: Add error for bad PACKAGE_PIN connectionsDavid Shah2018-10-031-2/+13
* clangformatDavid Shah2018-09-301-15/+23
* Merge pull request #79 from YosysHQ/ice40lvdsClifford Wolf2018-09-251-1/+1
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| * ice40: Tristate IO support fixesDavid Shah2018-09-241-1/+1
* | Merge pull request #76 from YosysHQ/plloutglobal_fixClifford Wolf2018-09-251-2/+36
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| * | Added required checks for PLL and fixed messages eolMiodrag Milanovic2018-09-191-3/+31
| * | Add needed PLLOUTGLOBAL ports and mapped it properlyMiodrag Milanovic2018-09-121-0/+6
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* / ice40: Fix carry packer bugDavid Shah2018-09-251-2/+2
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* ice40: make PLL packing more robustSergiusz Bazanski2018-08-191-11/+26
* Get rid of PortPin and BelType (ice40, generic, docs)Clifford Wolf2018-08-081-3/+3
* Fixing constraint placement bugsDavid Shah2018-08-031-2/+3
* Reworking packer and placer to use new generic rel legaliserDavid Shah2018-08-031-0/+3
* ice40: Promote 'logic' globals as well as clock/enable/resetDavid Shah2018-08-031-10/+40
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