Commit message (Collapse) | Author | Age | Files | Lines | |
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* | ice40: Switch from RelPtr to RelSlice | D. Shah | 2021-01-27 | 1 | -8/+5 |
| | | | | | | | | | | This replaces RelPtrs and a separate length field with a Rust-style slice containing both a pointer and a length; with bounds checking always enforced. Thus iterating over these structures is both cleaner and safer. Signed-off-by: D. Shah <dave@ds0.me> | ||||
* | ice40: Nicer error for unconstrained SB_GB_IO | David Shah | 2020-12-27 | 1 | -0/+2 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40: Clarify feedback paths in PLL constraints code | David Shah | 2020-12-03 | 1 | -3/+3 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40: Derive PLL timing constraints | David Shah | 2020-12-03 | 1 | -31/+138 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40/pack/SB_PLL: Force fixed value to 4'b1111 if dynamic delay is used | Sylvain Munaut | 2020-11-10 | 1 | -7/+9 |
| | | | | | | | | It's been confirmed that : (1) this is required by the hardware (2) icecube will force that field to 4'b1111 in fixed mode Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: If IO is used by SB_GB_IO, can't use it for PLL | Sylvain Munaut | 2020-07-09 | 1 | -1/+2 |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Derive oscillator frequency constraints | David Shah | 2020-03-29 | 1 | -0/+40 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40: Always copy DFF attrs to LC | David Shah | 2020-03-19 | 1 | -0/+5 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Preserve hierarchy through packing | David Shah | 2019-12-27 | 1 | -0/+1 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | frontend/generic: Fix regressions | David Shah | 2019-12-27 | 1 | -1/+3 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40: Preserve top level IO properly | David Shah | 2019-10-19 | 1 | -13/+3 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40: Add support for PLL DELAY_ADJUSTMENT_MODE | David Shah | 2019-09-23 | 1 | -1/+15 |
| | | | | | | Fixes #336 Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40: Move clock constraints across SB_IO and SB_GB_IO | David Shah | 2019-09-13 | 1 | -0/+20 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40: Add better stats on LC packing | David Shah | 2019-08-08 | 1 | -1/+11 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40: Fix regression | David Shah | 2019-08-05 | 1 | -1/+3 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Major Property improvements for common and iCE40 | David Shah | 2019-08-05 | 1 | -29/+31 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | clangformat run | Miodrag Milanovic | 2019-06-25 | 1 | -17/+15 |
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* | Merge master | Miodrag Milanovic | 2019-06-25 | 1 | -4/+33 |
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| * | clangformat | David Shah | 2019-06-24 | 1 | -3/+5 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | ice40: add RGB_DRV/LED_DRV_CUR support for u4k | Simon Schubert | 2019-06-10 | 1 | -4/+31 |
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* | | Use flags for each step | Miodrag Milanovic | 2019-06-14 | 1 | -1/+1 |
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* | | Save top level attrs and store current step | Miodrag Milanovic | 2019-06-07 | 1 | -0/+1 |
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* | | Add vcc and gnd nets and cells only if needed | Miodrag Milanovic | 2019-06-07 | 1 | -5/+20 |
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* | | WIP saving/loading attributes | Miodrag Milanovic | 2019-06-07 | 1 | -0/+1 |
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* | | Revert "Do not add VCC if not used, loading json works" | Miodrag Milanovic | 2019-06-02 | 1 | -6/+5 |
| | | | | | | | | This reverts commit f1b3a14bc23ccee6acaf6bbe27827523dc13c111. | ||||
* | | Added support for attributes/properties types | Miodrag Milanovic | 2019-06-01 | 1 | -1/+1 |
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* | | Do not add VCC if not used, loading json works | Miodrag Milanovic | 2019-05-31 | 1 | -5/+6 |
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* | ice40: Add support for HFOSC trimming | Sylvain Munaut | 2019-05-13 | 1 | -0/+5 |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Only create padin gbuf for PLLs if global output actually used | Sylvain Munaut | 2019-04-17 | 1 | -11/+38 |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Take placed SB_GBs into account when placing PLLs | Sylvain Munaut | 2019-04-16 | 1 | -9/+55 |
| | | | | | | | | | | | | | | | | Because the PLLs drive global networks, we need to account for already existing and placed SB_GBs when trying to place/pack them. Theses can be user instanciated SB_GBs with BEL attribute, or SB_GB_IOs that got converted during the IO packing. This patch assumes that: - If a PLL is used the output A global network is always used, even if there is no connection to the global output pin - If a PLL with a singe output is used, then the B output global network is still free to be used by whatever. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40/pack: During IO packing, remove any unused input connection | Sylvain Munaut | 2019-04-11 | 1 | -0/+13 |
| | | | | | | | | | This is mostly for the benefit of PLL placement because the D_IN_x ports are used for other purposes when PLL is enabled so we need to make sure nothing is connected there already. (even an unused net is too much) Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Don't constrain to a PLL bel that has already been used | David Shah | 2019-04-01 | 1 | -0/+2 |
| | | | | | | Fixes #258 Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40: Add support for SB_I2C and SB_SPI | Sylvain Munaut | 2019-03-25 | 1 | -1/+18 |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: PLLs can't conflict with themselves | David Shah | 2019-02-09 | 1 | -0/+2 |
| | | | | | | Fixes error building testcase from #145 Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40: Don't create PLLOUT_B buffer for single-output PLL variants | David Shah | 2019-02-09 | 1 | -1/+6 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Merge pull request #211 from smunaut/ice40_ram_attrs | David Shah | 2019-01-21 | 1 | -0/+4 |
|\ | | | | | ice40/pack: Copy attributes to packed cell | ||||
| * | ice40/pack: Copy attributes to packed RAM cells | Sylvain Munaut | 2019-01-19 | 1 | -0/+4 |
| | | | | | | | | | | | | | | Useful to allow manual placement of SPRAM/EBR using BEL attribute for instance Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | | ice40: Add error message if a selected site is not Global Buffer capable | Sylvain Munaut | 2019-01-18 | 1 | -0/+4 |
|/ | | | | | | ... rather than assert()-out during the call to getWireBelPins() call Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Improve handling of unconstrained IO | David Shah | 2018-12-26 | 1 | -3/+0 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40: Fix LOCK feedthrough insertion with carry or >8 LUTs | David Shah | 2018-12-20 | 1 | -4/+10 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | ice40: Report error for unsupported PLL FEEDBACK_PATH values | David Shah | 2018-12-06 | 1 | -7/+11 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40: add reset global promotion threshold. | whitequark | 2018-12-04 | 1 | -1/+3 |
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* | ice40: Add support for placing SB_LEDDA_IP block. | Daniel Serpell | 2018-12-01 | 1 | -0/+4 |
| | | | | Signed-off-by: Daniel Serpell <daniel.serpell@gmail.com> | ||||
* | ice40: Add a warning for unconstrained IO | David Shah | 2018-11-29 | 1 | -6/+5 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Merge pull request #157 from whitequark/fanout-thresh | David Shah | 2018-11-29 | 1 | -1/+1 |
|\ | | | | | ice40: raise CE global promotion threshold | ||||
| * | ice40: raise CE global promotion threshold. | whitequark | 2018-11-29 | 1 | -1/+1 |
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* | | ice40: print fanout of nets promoted to globals. | whitequark | 2018-11-28 | 1 | -7/+11 |
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* | ice40: Try to be helpful and suggest using PAD PLL instead of CORE | Sylvain Munaut | 2018-11-28 | 1 | -2/+14 |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Revamp the whole PLL placement/validity check logic | Sylvain Munaut | 2018-11-28 | 1 | -72/+200 |
| | | | | | | | | | | | | | | | | | We do a pre-pass on all the PLLs to place them before packing. To place them: - First pass with all the PADs PLLs since those can only fit at one specific BEL depending on the input connection - Second pass with all the dual outputs CORE PLLs. Those can go anywhere where there is no conflicts with their A & B outputs and used IO pins - Third pass with the single output CORE PLLs. Those have the least constrains. During theses passes, we also check the validity of all their connections. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Finer-grained control of global promotion | David Shah | 2018-11-27 | 1 | -2/+4 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> |