Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Switch to potentially-sparse net users array | gatecat | 2022-02-27 | 1 | -1/+1 |
| | | | | | | | | This uses a new data structure for net.users that allows gaps, so removing a port from a net is no longer an O(n) operation on the number of users the net has. Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | refactor: Use constids instead of id("..") | gatecat | 2022-02-16 | 1 | -45/+45 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | refactor: New NetInfo and CellInfo constructors | gatecat | 2022-02-16 | 1 | -3/+1 |
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* | Fixing old emails and names in copyrights | gatecat | 2021-06-12 | 1 | -3/+3 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Using hashlib in arches | gatecat | 2021-06-02 | 1 | -4/+4 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | ice40: Switch from RelPtr to RelSlice | D. Shah | 2021-01-27 | 1 | -21/+16 |
| | | | | | | | | | | This replaces RelPtrs and a separate length field with a Rust-style slice containing both a pointer and a length; with bounds checking always enforced. Thus iterating over these structures is both cleaner and safer. Signed-off-by: D. Shah <dave@ds0.me> | ||||
* | Fixes for new part types | Miodrag Milanovic | 2020-07-08 | 1 | -8/+20 |
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* | ice40: Add fallback behavior for Extra Cell config bits vectors | Sylvain Munaut | 2020-06-02 | 1 | -1/+11 |
| | | | | | | | This helps make new nextpnr compatible with old chipdbs when a parameters goes from single bit to multi bit. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Add support for the 2nd bit of SHIFTREG_DIV_MODE | Sylvain Munaut | 2020-06-02 | 1 | -1/+1 |
| | | | | | | This requires the matching chipdb update from icestorm project ! Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Improve error handling of Lattice-style parameters | David Shah | 2019-12-10 | 1 | -0/+3 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Major Property improvements for common and iCE40 | David Shah | 2019-08-05 | 1 | -29/+33 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | clangformat | David Shah | 2019-06-24 | 1 | -2/+3 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40: add RGB_DRV/LED_DRV_CUR support for u4k | Simon Schubert | 2019-06-10 | 1 | -0/+7 |
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* | ice40: Add support for SB_I2C and SB_SPI | Sylvain Munaut | 2019-03-25 | 1 | -0/+22 |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: support u4k | Simon Schubert | 2019-02-23 | 1 | -1/+11 |
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* | ice40: Add PCF support for -pullup, -pullup_resistor and -nowarn | David Shah | 2018-12-20 | 1 | -2/+15 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | ice40: Improve bitstream error handling | David Shah | 2018-12-06 | 1 | -2/+10 |
| | | | | | | Fixes #161 and provides a clearer error for #170 Signed-off-by: David Shah <dave@ds0.me> | ||||
* | clangformat | David Shah | 2018-12-06 | 1 | -1/+1 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40: Add support for placing SB_LEDDA_IP block. | Daniel Serpell | 2018-12-01 | 1 | -1/+2 |
| | | | | Signed-off-by: Daniel Serpell <daniel.serpell@gmail.com> | ||||
* | ice40: Update the way LVDS inputs are handled during bitstream generation | Sylvain Munaut | 2018-11-28 | 1 | -48/+48 |
| | | | | | | | | | | | | | | | * Instead of "patching" input_en, we completely separate config for normal and LVDS pair. - For normal pair, nothing changes - For LVDS pairs, the IE/REN bits are always set as if the input buffer are disabled. Then if input_en was set to 1 (i.e. the input is actually for something), then we set the IoCtrl.LVDS bit. - Also for LVDS, if input is used, pullups are forcibly disabled. * When scanning for unused IOs, never process those part of a LVDS pair. They will have been configured by the complement Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Add support for SB_RGBA_DRV | Sylvain Munaut | 2018-11-19 | 1 | -0/+5 |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Add support for SB_GB_IO | Sylvain Munaut | 2018-11-19 | 1 | -0/+1 |
| | | | | | | | | | | During packing we replace them by standard SB_IO cells and create the 'fake' SB_GB that matches that IO site global buffer connection. It's done in a separate pass because we need to make sure the nextpnr iob have been dealt first so we have our final Bel location on the SB_IO. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Add support for PLL global outputs via PADIN | Sylvain Munaut | 2018-11-19 | 1 | -44/+50 |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Introduce the concept of forPadIn SB_GB | Sylvain Munaut | 2018-11-19 | 1 | -1/+17 |
| | | | | | | | | | | | | | | Those are cells that are created mainly to handle the various sources a global network can be driven from other than a user net. When the flag is set, this means the global network usually driven by this BEL is in fact driven by something else and so that SB_GB BEL and matching global network can't be used. This is also what gets used to set the extra bits during bitstream generation. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40/bitstream: Handle IoCtrl.IE_ polarity when configuring unused SB_IO | Sylvain Munaut | 2018-11-19 | 1 | -2/+7 |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40/bitstream: Convert to UNIX line endings | Sylvain Munaut | 2018-11-16 | 1 | -1043/+1043 |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Remove unnecessary RAM assertion | David Shah | 2018-11-16 | 1 | -1/+0 |
| | | | | | | Fixes #121 Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40: Don't set colbuf bits for 384 | David Shah | 2018-11-11 | 1 | -0/+2 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | clangformat | David Shah | 2018-09-30 | 1 | -4/+1 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | ice40: LVDS input bitstream support | David Shah | 2018-09-24 | 1 | -4/+48 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | do not break if there are no nets loaded from sym section | Miodrag Milanovic | 2018-08-18 | 1 | -4/+6 |
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* | Get rid of PortPin and BelType (ice40, generic, docs) | Clifford Wolf | 2018-08-08 | 1 | -17/+17 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40) | Clifford Wolf | 2018-08-05 | 1 | -24/+24 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | clangformat | Clifford Wolf | 2018-08-05 | 1 | -21/+22 |
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* | ice40: Bitstream gen for LUT permutation | David Shah | 2018-08-04 | 1 | -8/+78 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | ice40: Add bitstream gen for routethru LUTs | David Shah | 2018-08-03 | 1 | -9/+58 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | ice40: Add HFOSC support, force fabric routing on oscillators for now | David Shah | 2018-08-01 | 1 | -0/+4 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | clangformat | Sergiusz Bazanski | 2018-08-01 | 1 | -2/+3 |
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* | clangformat | Eddie Hung | 2018-07-25 | 1 | -3/+2 |
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* | ice40: fixes before review | Sergiusz Bazanski | 2018-07-24 | 1 | -6/+6 |
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* | ice40: move PLL->IO from pseudo pip to second uphill bel | Sergiusz Bazanski | 2018-07-24 | 1 | -15/+16 |
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* | ice40: emit list of upbels in chipdb | Sergiusz Bazanski | 2018-07-24 | 1 | -1/+1 |
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* | clang-format | Sergiusz Bazanski | 2018-07-24 | 1 | -14/+21 |
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* | ice40: A slightly nicer way to do this. | Sergiusz Bazanski | 2018-07-24 | 1 | -46/+31 |
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* | ice40: Refactor PLL/LOCK LUT splicing out into Arch:: | Sergiusz Bazanski | 2018-07-24 | 1 | -0/+1 |
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* | ice40: Implement emitting PLLs | Sergiusz Bazanski | 2018-07-24 | 1 | -14/+104 |
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* | clangformat | David Shah | 2018-07-23 | 1 | -2/+3 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | Move to new API and remove deprecated | Miodrag Milanovic | 2018-07-22 | 1 | -36/+38 |
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* | Rename getWireBelPin to getBelPinWire | Clifford Wolf | 2018-07-22 | 1 | -3/+3 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Added driver and users for nets | Miodrag Milanovic | 2018-07-21 | 1 | -0/+8 |
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