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* | refactor: Use cell member functions to add portsgatecat2022-02-161-20/+14
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | refactor: New NetInfo and CellInfo constructorsgatecat2022-02-162-11/+5
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* | clangformatgatecat2022-02-161-7/+7
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* add GW1N-9C dbPepijn de Vos2022-02-061-1/+1
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* gowin: add an option to manually specify familyIcenowy Zheng2022-02-061-6/+11
| | | | | | | | | | | In the vendor IDE, there's a device family named GW1N-9C (which seems to mean C revision of GW1N-9), in which the model numbers are all the same with GW1N-9. Add an option to nextpnr-gowin to allow manually specified family for this situation. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* Merge pull request #906 from yrabbit/gowin-gui-nocgatecat2022-02-041-4/+4
|\ | | | | gowin: Speed up the GUI
| * gowin: Speed up the GUIYRabbit2022-02-041-4/+4
| | | | | | | | | | | | By mistake, an empty decal gets filled with graphical elements. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | gowin: Remove leftover debuggingYRabbit2022-02-041-1/+0
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge branch 'master' into diff-locationsYRabbit2022-02-048-17/+6527
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| * | run clangformatgatecat2022-02-031-1/+0
| |/ | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * gowin: Rearrange the GUI constantsYRabbit2022-02-032-4896/+4896
| | | | | | | | | | | | | | All internal constants for describing the graphics have been moved to the .cc file. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: Add GUI.YRabbit2022-01-298-17/+6528
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Items such as LUT, DFF, MUX, ALU, IOB are displayed; * Local wires, 1-2-4-8 wires are displayed; * The clock spines, taps and branches are displayed with some caveats. For now, you can not create a project in the GUI because of possible conflict with another PR (about GW1NR-9C support), but you can specify the board in the command line and load .JSON and .CST in the GUI. Although ALUs are displayed, but the CIN and COUT wires are not. This is still an unsolved problem. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | gowin: Add a DS location recognitionYRabbit2022-02-031-12/+18
|/ | | | | | | | | For differential signals it is necessary to set the position of two pins at once: P and N. This commit adds that capability and also adds another style of location setting --- with the pin letter in square brackets used in vendor tools. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Fix last MUX8YRabbit2022-01-031-1/+1
| | | | | | In fact, there is also an input/output column. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #877 from pepijndevos/patch-3gatecat2021-12-261-1/+1
|\ | | | | Add support for GW1NS-4 series devices
| * Add support for GW1NS-4 series devicesPepijn de Vos2021-12-241-1/+1
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* | gowin: Initializing the grid dimensionsYRabbit2021-12-261-1/+1
| | | | | | | | | | | | | | gridDimX and gridDimY are not initialized explicitly, which leads to effects when the design is reloaded, say, from the GUI. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | gowin: Add simplified IO cells processingYRabbit2021-12-204-4/+77
|/ | | | | | | | | | | | | | | Some models have I/O cells that are IOBUFs, and other types (IBUFs and OBUFs) are obtained by feeding 1 or 0 to the OEN input. This is done with general-purpose routing so it's best to do it here to avoid conflicts. For this purpose, in the new bases, these special cells are of type IOBS (IOB Simplified). The proposed changes are compatible with bases of previous versions of Apycula and do not require changing .CST constraint files. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-192-5/+6
| | | | | | | | | | | | This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me>
* Clean gowin modification regexuis2021-12-181-6/+2
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* gowin: Recognize models correctlyYRabbit2021-12-151-1/+1
| | | | | | | | | | | For example, clearly distinguish between GW1N-4 GW1NR-4 GW1NS-4 GW1NSR-4 GW1NSR-4 Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Fix spelling of messagesYRabbit2021-12-141-4/+4
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* clangformatgatecat2021-12-121-3/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* gowin: BUGFIX. Place the ALU head in sliсe 0 onlyYRabbit2021-12-111-0/+3
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Check the chipdb versionYRabbit2021-11-072-1/+7
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Use speed from chip base.YRabbit2021-11-053-20/+27
| | | | | | | Another simplification of the input regular expression, now the speed is taken from the base. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add partnumbers and packages to the chipdbYRabbit2021-11-043-6/+29
| | | | | | | | | | Instead of parsing the partnumber with a regular expression, a simple table is used. This is done because the structure of the partnumber changes as new features appear (e.g., ES instead of C6/I5) This commit does not yet disable the very first regular expression check. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Explicitly initialize the y in the clusterYRabbit2021-10-221-0/+5
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add ALU support.YRabbit2021-10-223-6/+221
| | | | | | | | - Both the mode used by yosys and all Gowin primitive modes are supported. - The ALU always starts with a zero slice. - The maximum length of the ALU chain is limited to one line of the chip. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin: more clearly mark dummy pipsPepijn de Vos2021-10-101-2/+2
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* gowin: Replace the zero delays with reasonable values.YRabbit2021-10-093-12/+40
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add support for wide LUTs.YRabbit2021-10-077-9/+434
| | | | | | | | | * A hardwired MUX within each logical cell is used. * The delay is equal 0. * No user placement constraints. * The output route contains dummy PIPs. They are ignored by gowin_pack, but it may be worth removing them. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Place DFFs of different types in the slice.YRabbit2021-08-311-2/+26
| | | | | | | | | | | | | | | | | Allow the registers of the same type or pairs shown below to be placed in the same slide: |--------|--------| | DFFS | DFFR | | DFFSE | DFFRE | | DFFP | DFFC | | DFFPE | DFFCE | | DFFNS | DFFNR | | DFFNSE | DFFNRE | | DFFNP | DFFNC | | DFFNPE | DFFNCE | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add constraints on primitive placement.YRabbit2021-08-313-14/+48
| | | | | | | | | | Added support for the INS_LOC instruction in the constraints file (.CST), which is used to specify object placement. Expanded treatment of IO_LOC/IO_PORT constraints, which now can be applied to both ports and IO buffers. Port constraints have priority. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add the IO[TRBL]style placement recognitionYRabbit2021-08-231-5/+37
| | | | | | | | | Specifying pin placement with this notation (e.g. IOR4B) allows to use the same constraint file without changes for different packages and even different families. The vendor router also understands this notation. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Change the constraint parser to support multiple options per line. ↵YRabbit2021-08-062-7/+14
| | | | | | Add support for IOBUF and TBUF I/O modes. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* clangformatgatecat2021-07-211-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* remove generic leftover in gowinPepijn de Vos2021-07-171-2/+0
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* GW1NR is not a seperate family, but GW1NS isPepijn de Vos2021-07-111-1/+8
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* Merge pull request #755 from yrabbit/io_portgatecat2021-07-081-16/+24
|\ | | | | Pin modes parser
| * Fix the boolean.YRabbit2021-07-081-1/+1
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * Fix formatingYRabbit2021-07-071-24/+24
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * Fix boolean value.YRabbit2021-07-071-1/+1
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * Merge branch 'master' into io_portYRabbit2021-07-072-6/+7
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| * | Wip parserYRabbit2021-07-071-16/+4
| | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * | ParserYRabbit2021-07-051-0/+9
| | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * | Fix parser. Comments and IO_PORTYRabbit2021-07-031-11/+9
| | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * | SyntaxYRabbit2021-07-021-3/+3
| | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * | Add IO_PORT parsingYRabbit2021-07-021-14/+27
| | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | | clangformatgatecat2021-07-081-2/+1
| |/ |/| | | | | Signed-off-by: gatecat <gatecat@ds0.me>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 18:05:07 +0000