| Commit message (Collapse) | Author | Age | Files | Lines |
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The model should be recognized by the partnumber, --family is needed
only if the same partnumbers belong to different models.
This is done in order to automatically generate parameters for calling
nextpnr from Gowin files without problems: there also only partnumber is
used and only in some cases the model is specified with the -name
parameter and GW1NZ-1 is not such a case.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Signed-off-by: gatecat <gatecat@ds0.me>
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In the vendor IDE, there's a device family named GW1N-9C (which seems to
mean C revision of GW1N-9), in which the model numbers are all the same
with GW1N-9.
Add an option to nextpnr-gowin to allow manually specified family for
this situation.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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* Items such as LUT, DFF, MUX, ALU, IOB are displayed;
* Local wires, 1-2-4-8 wires are displayed;
* The clock spines, taps and branches are displayed with some caveats.
For now, you can not create a project in the GUI because of possible
conflict with another PR (about GW1NR-9C support), but you can specify
the board in the command line and load .JSON and .CST in the GUI.
Although ALUs are displayed, but the CIN and COUT wires are not. This is
still an unsolved problem.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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For example, clearly distinguish between
GW1N-4
GW1NR-4
GW1NS-4
GW1NSR-4
GW1NSR-4
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Another simplification of the input regular expression, now
the speed is taken from the base.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Instead of parsing the partnumber with a regular expression,
a simple table is used. This is done because the structure
of the partnumber changes as new features appear (e.g., ES instead of C6/I5)
This commit does not yet disable the very first regular expression check.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: David Shah <dave@ds0.me>
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* load wires
* add slice bels
* add IOB
* add aliases
* local aliases
* broken packing stuff
* working packer
* add constraints
* pnr runs1111
* add timing info
* constraints
* more constraint stuff
* add copyright
* remove generic reference
* remove parameters
* remove generic python api
* add newline to end of file
* some small refactoring
* warn on invalid constraints
* don't error on missing cell
* comment out debugging print
* typo
* avoid copy
* faster empty idstring
* remove intermediate variable
* no more deadnames
* fix cst warnings
* increase ripup and epsilon a bit
* take single device parameter
* add info to readme
* gui stubs
* Revert 4d03b681a8634e978bd5af73c97665500047e055
* assign ff_used in assignArchInfo
* decrease beta for better routability
* try to fix CI
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