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* Fixing old emails and names in copyrightsgatecat2021-06-121-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib for core netlist structuresgatecat2021-06-021-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add "checkPipAvailForNet" to Arch API.Keith Rothman2021-03-221-0/+6
| | | | | | | | This is important for distiguishing valid pseudo pips in the FPGA interchange arch. This also avoids a double or triple lookup of pip->net map. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Change CellInfo in getBelPinsForCellPin to be const.Keith Rothman2021-02-231-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-11/+10
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* Remove isValidBelForCellgatecat2021-02-161-15/+0
| | | | | | | | | | | | | | | | | This Arch API dates from when we were first working out how to implement placement validity checking, and in practice is little used by the core parts of placer1/HeAP and the Arch implementation involves a lot of duplication with isBelLocationValid. In the short term; placement validity checking is better served by the combination of checkBelAvail and isValidBelForCellType before placement; followed by isBelLocationValid after placement (potentially after moving/swapping multiple cells). Longer term, removing this API makes things a bit cleaner for a new validity checking API. Signed-off-by: gatecat <gatecat@ds0.me>
* generic: Add APIs for controlling cell->bel pin mappinggatecat2021-02-151-1/+14
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #575 from YosysHQ/gatecat/belpin-2gatecat2021-02-151-0/+2
|\ | | | | Support for cell pin to bel pin mappings
| * Add getBelPinsForCellPin to Arch APIgatecat2021-02-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | This is a basic implementation, without considering "M of N" arrangements (e.g. for LUT permuation where you only want to route to 1 out of 4/6 sinks) or using a type other than IdString to identify bel pins. But this is also enough to start working out where in nextpnr will break due to removing the 1:1 cell:bel pin cardinality, as a next step. Signed-off-by: gatecat <gatecat@ds0.me>
* | Add getBelHidden and add some missing "override" statements.Keith Rothman2021-02-111-1/+4
|/ | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* generic: Fix pin names accidentally being IdStringList not IdStringD. Shah2021-02-051-3/+3
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Mark IdString and IdStringList single argument constructors explicit.Keith Rothman2021-02-041-11/+8
| | | | | | | | | Single argument constructors will silently convert to that type. This is typically not the right thing to do. For example, the nexus and ice40 arch_pybindings.h files were incorrectly parsing bel name strings, etc. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* generic: Use IdStringList for all arch object namesD. Shah2021-02-021-34/+40
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Remove wire alias APIDavid Shah2020-10-151-16/+0
| | | | | | It has not actually been implemented in any router for over 2.5 years and causes nothing more than confusion. It can always be added back if it forms part of a future solution; possibly as part of a more general database structure rethink. Signed-off-by: David Shah <dave@ds0.me>
* generic: Implement getRouteBoundingBoxDavid Shah2020-02-031-0/+24
| | | | Signed-off-by: David Shah <dave@ds0.me>
* router2: Improve flow and log outputDavid Shah2020-02-031-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Allow selection of router algorithmDavid Shah2020-02-031-2/+16
| | | | Signed-off-by: David Shah <dave@ds0.me>
* generic: Improve error handling when Wire/Pip/Bel is not foundDavid Shah2019-11-271-21/+45
| | | | Signed-off-by: David Shah <dave@ds0.me>
* generic: Use HeAP as placer where possibleDavid Shah2019-11-261-3/+33
| | | | Signed-off-by: David Shah <dave@ds0.me>
* generic: New Property interfaceDavid Shah2019-08-051-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* clangformat runMiodrag Milanovic2019-06-251-1/+2
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* Use flags for each stepMiodrag Milanovic2019-06-141-2/+2
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* Save top level attrs and store current stepMiodrag Milanovic2019-06-071-2/+10
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* CleanupMiodrag Milanovic2019-06-071-11/+0
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* WIP saving/loading attributesMiodrag Milanovic2019-06-071-0/+11
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* generic: Fix predictDelayDavid Shah2019-04-041-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* generic: Cell timing supportDavid Shah2019-04-041-6/+59
| | | | Signed-off-by: David Shah <dave@ds0.me>
* generic: GUI Python bindingsDavid Shah2019-04-031-2/+12
| | | | Signed-off-by: David Shah <dave@ds0.me>
* generic: Simple procedural example worksDavid Shah2019-04-021-3/+9
| | | | Signed-off-by: David Shah <dave@ds0.me>
* generic: Add a simple packer for generic SLICEs and IOBsDavid Shah2019-04-021-2/+70
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Add --placer option and refactor placer selectionDavid Shah2019-03-241-1/+14
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-131-0/+2
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| * Add getConflictingPipWire() arch API, router1 improvementsClifford Wolf2018-11-111-0/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | generic: Update arch to new timing APIDavid Shah2018-11-121-1/+6
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* clangformatDavid Shah2018-09-301-12/+3
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Merge pull request #47 from YosysHQ/settings_propagateClifford Wolf2018-08-181-2/+2
|\ | | | | Use settings for placer1 and router1
| * Use settings for placer1 and router1Miodrag Milanovic2018-08-091-2/+2
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* | Add Arch attrs APIClifford Wolf2018-08-141-0/+21
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add pip locationsClifford Wolf2018-08-091-6/+19
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'master' of github.com:YosysHQ/nextpnr into constidsClifford Wolf2018-08-081-4/+6
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| * Merge pull request #44 from YosysHQ/improve_timing_specDavid Shah2018-08-081-3/+5
| |\ | | | | | | Speed up budget allocator using topographical ordering and update cell timing API
| | * Arch API: New specification for timing port classesDavid Shah2018-08-081-3/+5
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * Modify getBudgetOverride for generic and ecp5 tooEddie Hung2018-08-051-1/+1
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| * | Merge remote-tracking branch 'origin/master' into common_mainMiodrag Milanovic2018-08-081-28/+28
| |\ \ | | | | | | | | | | | | | | | | | | | | # Conflicts: # ecp5/main.cc # ice40/main.cc
| * | | Added project loaderMiodrag Milanovic2018-08-061-1/+1
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* | | | Get rid of BelType and PortPin in generic archClifford Wolf2018-08-081-5/+5
| |/ / |/| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Modify getBudgetOverride for generic and ecp5 tooEddie Hung2018-08-061-1/+1
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* | API change: Use CellInfo* and NetInfo* as cell/net handles (generic)Clifford Wolf2018-08-051-27/+27
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* compile fixMiodrag Milanovic2018-08-041-1/+1
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* Merge pull request #33 from YosysHQ/gui-ecp5Miodrag Milanović2018-08-041-1/+1
|\ | | | | Gui ecp5
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